IDT71B74 Search Results

Contextual Info: INTEGRATED DEVICE bbE D 4Ô2S771 GQ1E367 DIE • IDT BiCMOS STATIC RAM 64k 8k x 8-BIT CACHE-TAG RAM IDT71B74 Integrated Device Technology, Inc« FEATURES: DESCRIPTION: • High-speed address to MATCH comparison time — Commercial: 10/12/15/20ns (max.) • High-speed address access time

74S107

Contextual Info: BiCMOS STATIC RAM 64K 8K x 8-BIT CACHE-TAG RAM IDT71B74 In te g ra te d D evice T ec hnology, In c . FEATURES: DESCRIPTION: • H igh-speed ad dress to M A TC H com parison tim e — C om m ercia l: 8/1 0/12 /15/20ns (m ax.) • H igh-speed ad dress acce ss tim e

TAA 521 A

Abstract: TAA 521
Contextual Info: CMOS STATIC RAM 64K 8K x 8-BIT CACHE-TAG RAM IDT7174S NOT RECOMMENDED FOR NEW DESIGNS SEE IDT71B74 PAGE 6.15 FEATURES: DESCRIPTION: • H ig h -sp e e d a d d re s s to M A T C H c o m p a ris o n tim e — M ilitary: 3 5 /4 5 /5 5 n s (m ax.) — C o m m e rc ia l: 3 0 /3 5 /4 5 n s (m ax.)

71B74

Abstract: 71B74S15 AN78
Contextual Info: IDT71B74 BiCMOS STATIC RAM 64K 8K x 8-BIT CACHE-TAG RAM Integrated Device Technology, Inc. FEATURES: DESCRIPTION: • High-speed address to MATCH comparison time — Commercial: 8/10/12/15/20ns (max.) • High-speed address access time — Commercial: 8/10/12/15/20ns (max.)

74S12

Contextual Info: Integrated Device Technology, Inc. BiCMOS STATIC RAM 64K 8K x 8-BIT CACHE-TAG RAM PRELIMINARY INFORMATION IDT71B74 FEATURES: DESCRIPTION: • High-speed address to M A T C H comparison time — Military: 15/18/25ns (max.) — Commercial: 1 2 /1 5 /I8 n s (max.)

0-022O

Abstract: AN78
Contextual Info: BiCMOS STATIC RAM 64K 8K x 8-BIT CACHE-TAG RAM IDT71B74 Integrated D evice Technology, Inc. FEATURES: DESCRIPTION: • High-speed address to M ATCH comparison time — Commercial: 8/10/12/15/20ns (max.) • High-speed address access time — Commercial: 8/10/12/15/20ns (max.)

L7C174WC-15

Contextual Info: L7C174 8K x 8 Cache-Tag Static RAM FEATURES DESCRIPTION □ 8K x 8 CMOS Static RAM with 8-bit Tag Comparison Logic □ High Speed Address-to-MATCH — 12 ns maximum □ High Speed Flash Clear □ High Speed Read Access Time — 12 ns maximum □ Low Power Operation

E5CW

Contextual Info: Integrated Device Technology, Inc. 256KB AND 512KB SECONDARY CACHE MODULES FOR THE INTEL' PENTIUM CPU AND VLSI WILDCAT CORE LOGIC FEATURES PRELIMINARY IDT7MPV6239 IDT7MPV6240 IDT7MPV6241 IDT7MPV6244 high-speed 16-bit IDT FCT logic, and the IDT7MPV6241/44

L7C174WC-15

Abstract: idt7174 l7c174wc15 L7C174CM20 L7C174WC25
Contextual Info: L7C174 L7C174 DEVICES INCORPORATED 8K x 8 Cache-Tag Static RAM 8K x 8 Cache-Tag Static RAM DEVICES INCORPORATED FEATURES DESCRIPTION ❑ Low Power Operation Active: 300 mW typical at 35 ns Standby: 500 µW typical ❑ Data Retention at 2 V for Battery Backup Operation

Contextual Info: L7C174 8K x 8 Cache-Tag S tatic RAM D E V IC E S IN C O R P O R A TE D FEATURES □ 8K x 8 CMOS Static RAM with 8-bit Tag Comparison Logic □ High Speed Address-to-MATCH — 12 ns maximum □ High Speed Flash Clear □ High Speed Read Access Time — 12 ns maximum

Contextual Info: ^aaai^ _»l <•■■ ;s■■s » Galileo ■■ Technology, Inc. Secondary Cache Controller For The R4600/R4700 GT-64012 Preliminary December 1995/Rev. 2 NOTE: Always contact Galileo Technology for possible updates before starting a design. FEATURES Secondary cache controller for the 64-bit IDT R4600

Contextual Info: b4E D L O O lO 1 LOGIC B DEVICES INC • □ 8K x 8 CMOS Static RAM with 8-bit Tag Comparison Logic □ High Speed Address-to-MATCH — 12 ns maximum □ High Speed Flash Clear □ High Speed Read Access Time — 12 ns maximum □ Low Power Operation Active: 320 mW typical at 35 ns

Contextual Info: R I n te g r a te d D e v ic e T e c h n o lo g y , In c . BiCMOS STATIC RAM 64K (8K x 8-BIT) CACHE-TAG RAM FEA TU R ES: ID T 71B 74 D ES C R IPTIO N : • High-speed address to MATCH comparison time — Commercial: 8/10/12/15/20ns (max.) • High-speed address access time

vlsi

Abstract: IDT71B74 VLSI free
Contextual Info: N R E W S E L E A S E FOR IMMEDIATE RELEASE FOR FURTHER INFORMATION: Tami Maggio, Public Relations Specialist Steve Eliscu, Subsystems Marketing Manager 408 492-8699 (408) 456-2315 IDT INTRODUCES CACHE MODULE FAMILY FOR VLSI’S WILDCAT CHIPSET 66MHz Modules Support Wildcat-based 3.3-volt Pentium Systems

m25j

Contextual Info: 128KB SECONDARY CACHE MODULE FOR THE INTEL i486™ PRELIMINARY IDT7MB6091 Integrated Device Technology, Inc. FEATURES: DESCRIPTION: • Pin compatible with the Intel 485Turbocache™ 82485MB The IDT7MB6091 is a pin compatible replacement for the Intel 485Turbocache™ 82485MB. The module is a 128KB

Contextual Info: L7C174 8K x 8 Cache-Tag Static RAM DEVICES INCORPORATED DESCRIPTION FEATURES □ 8K x 8 CMOS Static RAM w ith 8-bit Tag Comparison Logic □ High Speed Address-to-MATCH — 12 ns maximum □ High Speed Flash Clear □ High Speed Read Access Time — 12 ns maximum

IDT7MP6104

Contextual Info: 128KB/256KB SECONDARY CACHE MODULE FOR THE INTEL i486 “ IDT7MP6104 IDT7MP6105 Integrated D evice T ech n olo g y, Inc. FEATURES DESCRIPTION • 128KB/256KB direct mapped, write-through, non-sectored, zero-wait-state secondary cache module • Ideal for use with ¡486-based systems

6104d

Abstract: IDT7MB6098
Contextual Info: IDT7MB6098A 128KB SECONDARY CACHE MODULE FOR THE INTEL* i486” FEATURES DESCRIPTION • Pin c o m patible w ith th e Intel 485TurboC ache 82485M B • 128KB dire ct m a pped , w rite -th ro u g h , non-sectored , zerow a it-s ta te sec o n d a ry ca ch e m odule

Contextual Info: L7C174 8K x 8 Cache-Tag Static RAM FEATURES_ □ 8K x 8 CMOS Static RAM with 8-bit Tag Comparison Logic □ High Speed Address-to-MATCH — 12 ns maximum □ High Speed Flash Clear □ High Speed Read Access Time — 12 ns maximum □ Low Power Operation

Contextual Info: 3ÛE D I N T E G R A T E D DEVI CE • MÔSS771 DGQÔMOÔ 1 ■ T - BiCMOS STATIC RAM ^ '2 - 3 - 1 2 . P R E L IM IN A R Y IN F O R M A TIO N |DT71 B?4 r k v q n i" n 6 4 K 8 K X 8 - B IT raw Integrated Device Technology, Inc. IDT CACHE-TAGRAM FEA TUR ES:

idt 256kb cache

Abstract: 7MP610
Contextual Info: bfiE D 1P x * 1dt Integrated Device Technology, Inc. • 4555771 D014S31 71S ■ IDT IDT7MP6104 128KB/256KB SECONDARY CACHE MODULE IDT7MP6105 FOR THE INTEL i486 INTEGRATED DEVICE FEATURES DESCRIPTION • 128KB/256KB direct mapped, write-through, non-sectored,

IDT7174

Abstract: IDT71B74 L7C174PC12 L7C174PC15 L7C174PC20 L7C174PC25 L7C174WC
Contextual Info: L7C174 L7C174 DEVICES INCORPORATED 8K x 8 Cache-Tag Static RAM 8K x 8 Cache-Tag Static RAM DEVICES INCORPORATED FEATURES DESCRIPTION ❑ 8K x 8 CMOS Static RAM with 8-bit Tag Comparison Logic ❑ High Speed Address-to-MATCH — 12 ns maximum ❑ High Speed Flash Clear

Contextual Info: L7C174 8K x 8 Cache-Tag Static RAM FEATURES D E S C R IP T IO N □ 8K x 8 CMOS Static RAM with 8-bit Tag Comparison Logic □ High Speed Address-to-MATCH — 12 ns maximum □ High Speed Flash Clear □ High Speed Read Access Time — 12 ns maximum □ Low Power Operation

Contextual Info: 1 7CA 7à L7C174 8K x 8 Cache-Tag Static RAM DEVICES INCORPORATED FEATURES □ 8K x 8 CMOS Static RAM with 8-bit Tag Comparison Logic □ High Speed Address-to-MATCH — 12 ns maximum □ High Speed Flash Clear □ High Speed Read Access Time — 12 ns maximum