IDT71B74 Search Results

Contextual Info: INTEGRATED DEVICE bbE D 4Ô2S771 GQ1E367 DIE • IDT BiCMOS STATIC RAM 64k 8k x 8-BIT CACHE-TAG RAM IDT71B74 Integrated Device Technology, Inc« FEATURES: DESCRIPTION: • High-speed address to MATCH comparison time — Commercial: 10/12/15/20ns (max.) • High-speed address access time

74S107

Contextual Info: BiCMOS STATIC RAM 64K 8K x 8-BIT CACHE-TAG RAM IDT71B74 In te g ra te d D evice T ec hnology, In c . FEATURES: DESCRIPTION: • H igh-speed ad dress to M A TC H com parison tim e — C om m ercia l: 8/1 0/12 /15/20ns (m ax.) • H igh-speed ad dress acce ss tim e

80486 microprocessor pin out diagram

Abstract: 80486 microprocessor block diagram and pin diagram 71B74 80486 memory devices IDT71B74 P28-2
Contextual Info: IDT71B74 BiCMOS STATIC RAM 64K 8K x 8-BIT CACHE-TAG RAM Integrated Device Technology, Inc. FEATURES: DESCRIPTION: • High-speed address to MATCH comparison time — Commercial: 8/10/12/15/20ns (max.) • High-speed address access time — Commercial: 8/10/12/15/20ns (max.)

intel 80486 architecture

Abstract: architecture of 80486 block diagram of processor 80486 80486* diagram circuits intel 80486 80486 pinout diagram 80486 80486 architecture TAG A3 idt p28-2
Contextual Info:  80486 Secondary Burst Cache Design Using IDT71B74 Cache-Tag SRAMs and IDT71256 Cache-Data SRAMs Application Brief AB-03 Integrated Device Technology, Inc. INTRODUCTION The objective of this application brief is to highlight the IDT71B74 8K x 8 Cache-Tag SRAM as the Cache-Tag SRAM in

TAA 521 A

Abstract: TAA 521
Contextual Info: CMOS STATIC RAM 64K 8K x 8-BIT CACHE-TAG RAM IDT7174S NOT RECOMMENDED FOR NEW DESIGNS SEE IDT71B74 PAGE 6.15 FEATURES: DESCRIPTION: • H ig h -sp e e d a d d re s s to M A T C H c o m p a ris o n tim e — M ilitary: 3 5 /4 5 /5 5 n s (m ax.) — C o m m e rc ia l: 3 0 /3 5 /4 5 n s (m ax.)

71B74

Abstract: 71B74S15 AN78
Contextual Info: IDT71B74 BiCMOS STATIC RAM 64K 8K x 8-BIT CACHE-TAG RAM Integrated Device Technology, Inc. FEATURES: DESCRIPTION: • High-speed address to MATCH comparison time — Commercial: 8/10/12/15/20ns (max.) • High-speed address access time — Commercial: 8/10/12/15/20ns (max.)

din 2982

Abstract: IDT7174S TAA 521 A IDT7174 I2114 TAA 521
Contextual Info: CMOS STATIC RAM 64K 8K x 8-BIT CACHE-TAG RAM IDT7174S NOT RECOMMENDED FOR NEW DESIGNS SEE IDT71B74 PAGE 6.15 FEATURES: DESCRIPTION: • H ig h -sp e e d ad d re s s to M A T C H co m p a ris o n tim e — M ilitary: 3 5 /4 5 /5 5 n s (m ax.) — C o m m e rc ia l: 3 0 /3 5 /4 5 n s (m ax.)

74S12

Contextual Info: Integrated Device Technology, Inc. BiCMOS STATIC RAM 64K 8K x 8-BIT CACHE-TAG RAM PRELIMINARY INFORMATION IDT71B74 FEATURES: DESCRIPTION: • High-speed address to M A T C H comparison time — Military: 15/18/25ns (max.) — Commercial: 1 2 /1 5 /I8 n s (max.)

0-022O

Abstract: AN78
Contextual Info: BiCMOS STATIC RAM 64K 8K x 8-BIT CACHE-TAG RAM IDT71B74 Integrated D evice Technology, Inc. FEATURES: DESCRIPTION: • High-speed address to M ATCH comparison time — Commercial: 8/10/12/15/20ns (max.) • High-speed address access time — Commercial: 8/10/12/15/20ns (max.)

idt7174

Abstract: TAA 521 TAA 521 A
Contextual Info: Integrated Device Technology, Inc* CMOS STATIC RAM 64K 8K x 8-BIT CACHE-TAG RAM IDT7174S NOT RECOMMENDED FOR NEW DESIGNS SEE IDT71B74 PAGE 6.15 FEATURES: DESCRIPTION: • High-speed address to MATCH comparison time — Military: 35/45/55ns (max.) — Commercial: 30/35/45ns (max.)

Contextual Info: Integrated Device Technology, Inc. BiCMOS STATIC RAM 64K 8K x 8-BIT CACHE-TAG RAM PRELIMINARY INFORMATION IDT71B74 FEATURES: DESCRIPTION: • High-speed address to MATCH comparison time — Military: 15/18/25ns (max.) — Commercial: 12/15/18ns (max.) • High-speed address access time

Contextual Info: mS»"\ R l BiCMOS STATIC RAM 64K 8K x 8-BIT CACHE-TAG RAM IDT71B74 Integrated Device Technology, Inc. FEATURES: DESCRIPTION: • H igh-spee d a d d re s s to M A T C H c o m p a ris o n tim e — C o m m e rc ia l: 8 /1 0 /1 2 /1 5/2 0ns (m ax.) • H igh-spee d a d d re s s a c c e s s tim e

71B74

Contextual Info: BiCMOS STATIC RAM 64K 8K x 8-BIT CACHE-TAG RAM IDT71B74 Integrated Device Technology, Inc. FEATURES: DESCRIPTION: • High-speed address to MATCH comparison time — Commercial: 8/10/12/15/20ns (max.) • High-speed address access time — Commercial: 8/10/12/15/20ns (max.)

B589

Abstract: b589 datasheet 71B74 80486 microprocessor block diagram and pin diagram B-589 80486 microprocessor description 80486 microprocessor pin out diagram IDT71B74 P28-2
Contextual Info:  IDT71B74 BiCMOS STATIC RAM 64K 8K x 8-BIT CACHE-TAG RAM Integrated Device Technology, Inc. FEATURES: DESCRIPTION: • High-speed address to MATCH comparison time — Commercial: 8/10/12/15/20ns (max.) • High-speed address access time — Commercial: 8/10/12/15/20ns (max.)

L7C174WC-15

Contextual Info: L7C174 8K x 8 Cache-Tag Static RAM FEATURES DESCRIPTION □ 8K x 8 CMOS Static RAM with 8-bit Tag Comparison Logic □ High Speed Address-to-MATCH — 12 ns maximum □ High Speed Flash Clear □ High Speed Read Access Time — 12 ns maximum □ Low Power Operation

E5CW

Contextual Info: Integrated Device Technology, Inc. 256KB AND 512KB SECONDARY CACHE MODULES FOR THE INTEL' PENTIUM CPU AND VLSI WILDCAT CORE LOGIC FEATURES PRELIMINARY IDT7MPV6239 IDT7MPV6240 IDT7MPV6241 IDT7MPV6244 high-speed 16-bit IDT FCT logic, and the IDT7MPV6241/44

L7C174WC-15

Abstract: idt7174 l7c174wc15 L7C174CM20 L7C174WC25
Contextual Info: L7C174 L7C174 DEVICES INCORPORATED 8K x 8 Cache-Tag Static RAM 8K x 8 Cache-Tag Static RAM DEVICES INCORPORATED FEATURES DESCRIPTION ❑ Low Power Operation Active: 300 mW typical at 35 ns Standby: 500 µW typical ❑ Data Retention at 2 V for Battery Backup Operation

Contextual Info: L7C174 8K x 8 Cache-Tag S tatic RAM D E V IC E S IN C O R P O R A TE D FEATURES □ 8K x 8 CMOS Static RAM with 8-bit Tag Comparison Logic □ High Speed Address-to-MATCH — 12 ns maximum □ High Speed Flash Clear □ High Speed Read Access Time — 12 ns maximum

mips r4600

Abstract: SRAM 256KB 6ns QS3383Q R4700-150MHz M 0737
Contextual Info: .< 1 1 1 ^ GT-64012/A ija li lea Secondary Cache Controller for R4600/4650/4700/5000 P lease contact Galileo Technology for possible updates before finalizing a design. FEATURES • • • • • • • • • • • Final Revision 3.0 10/22/97 Supports all write patterns DDDD or slower

intel i486

Abstract: IDT7MP6105 7MP6104
Contextual Info: bfiE D I S^N. • • Haas77i a n m s 3 i ?is ■ idt IDT7MP6104 128KB/256KB SECONDARY CACHE MODULE IDT7MP6105 FOR THE INTEL i486 INTEGRATED DEVICE Integrated Device Technology, Inc* FEATURES DESCRIPTION • 128 K B /2 5 6 K B d ire c t m a pped , w rite -th ro u g h , no n-sectored ,

Contextual Info: ^aaai^ _»l <•■■ ;s■■s » Galileo ■■ Technology, Inc. Secondary Cache Controller For The R4600/R4700 GT-64012 Preliminary December 1995/Rev. 2 NOTE: Always contact Galileo Technology for possible updates before starting a design. FEATURES Secondary cache controller for the 64-bit IDT R4600

Contextual Info: b4E D L O O lO 1 LOGIC B DEVICES INC • □ 8K x 8 CMOS Static RAM with 8-bit Tag Comparison Logic □ High Speed Address-to-MATCH — 12 ns maximum □ High Speed Flash Clear □ High Speed Read Access Time — 12 ns maximum □ Low Power Operation Active: 320 mW typical at 35 ns

Contextual Info: R I n te g r a te d D e v ic e T e c h n o lo g y , In c . BiCMOS STATIC RAM 64K (8K x 8-BIT) CACHE-TAG RAM FEA TU R ES: ID T 71B 74 D ES C R IPTIO N : • High-speed address to MATCH comparison time — Commercial: 8/10/12/15/20ns (max.) • High-speed address access time

vlsi

Abstract: IDT71B74 VLSI free
Contextual Info: N R E W S E L E A S E FOR IMMEDIATE RELEASE FOR FURTHER INFORMATION: Tami Maggio, Public Relations Specialist Steve Eliscu, Subsystems Marketing Manager 408 492-8699 (408) 456-2315 IDT INTRODUCES CACHE MODULE FAMILY FOR VLSI’S WILDCAT CHIPSET 66MHz Modules Support Wildcat-based 3.3-volt Pentium Systems