VDD16 Search Results

Contextual Info: SMJ320C50/SMQ320C50 DIGITAL SIGNAL PROCESSOR SGUS020B – JUNE 1996 – REVISED SEPTEMBER 2001 D Military Operating Temperature Range: D D D D D D D D D D D D D D D D D ÉÉ ÉÉ 100 132 ÉÉ ÉÉ 1 99 33 67 ÉÉ ÉÉ 66 D ÉÉ ÉÉ ÉÉ ÉÉ 34 D D – 55°C to 125°C

2SK2493

Contextual Info: TOSHIBA 2SK2493 TOSHIBA FIELD EFFECT TRANSISTOR SILICON N CHANNEL MOS TYPE tt-M O SV 2SK2493 HIGH SPEED, HIGH CURRENT SWITCHING APPLICATIONS CHOPPER REGULATOR, AND DC-DC CONVERTER APPLICATIONS INDUSTRIAL APPLICATIONS Unit in mm j 2.5V Gate Drive Low Drain-Source ON Resistance : RßS (ON)= 0.08mil (Typ.)

Myson MTD972

Abstract: 10BASET 20MHZ MTD972 1b.9 MYSON TECHNOLOGY
Contextual Info: MTD972 Preliminary MYSON TECHNOLOGY 100BaseTX PCS/PMA FEATURES • · · · · · · · · · · IEEE 802.3 10BaseT and 802.3u 100BaseTx compliant. MII interface with serial management. Auto negotiation compatible with next page capability. 100BaseTx PCS/PMA function with on-chip clock generation and recovery.

CRYSTAL 20 mhZ

Abstract: Crystal oscillator 12 MHz 130Q 1N3600 604D PCK604S
Contextual Info: OM C HI P SEE D S YSTEMS bT' l OLi S? 0000M47 OCS SD2 PCK604 ^ 5 0 - 0 ^ 50 to 600 MHz Crystal Controlled Frequency Synthesizer OnChip Systems P R O D U C T H IG H L IG H T S 50 - 600 MHz ♦ F requency Range 50 to 6 0 0 MHz 12.5-18.75 MHz CRYSTAL ♦ Inexpensive In p u t C rystal 12.5 to

Contextual Info: SM320C50ĆEP DIGITAL SIGNAL PROCESSOR SGUS040A − AUGUST 2002 − REVISED JANUARY 2006 D Controlled Baseline D D D D D D D D D D D PQ PACKAGE TOP VIEW − One Assembly/Test Site, One Fabrication Site Enhanced Diminishing Manufacturing Sources (DMS) Support

Contextual Info: SMJ320C50/SMQ320C50 DIGITAL SIGNAL PROCESSOR SGUS020B - JUNE 1996 - REVISED SEPTEMBER 2001 D Military Operating Temperature Range: D D D D D D D D D D D D D D D D D 100 132 1 33 66 D 34 D D - 55°C to 125°C Processed to MIL-PRF-38535 Fast Instruction Cycle Time 30 ns and

ac voltage stabilizer circuit diagram

Abstract: LVDS fin 1002 D1557 LTC1461 marking code G46 DB9 pin configuration lvds 32 pin LTC2208 LTC2216 LTC2217
Contextual Info: LTC2216/LTC2215 16-Bit, 80Msps/65Msps Low Noise ADC DESCRIPTION FEATURES n n n n n n n n n n n n n n n The LTC 2216/LTC2215 are 80Msps/65Msps sampling 16bit A/D converters designed for digitizing high frequency, wide dynamic range signals with input frequencies up to

Contextual Info: SM320C50ĆEP DIGITAL SIGNAL PROCESSOR SGUS040A − AUGUST 2002 − REVISED JANUARY 2006 D Controlled Baseline D D D D D D D D D D D PQ PACKAGE TOP VIEW − One Assembly/Test Site, One Fabrication Site Enhanced Diminishing Manufacturing Sources (DMS) Support

SMJ320C50

Abstract: SMJ320C50GFAM50 SMJ320C50GFAM66 SMJ320C50HFGM50 SMJ320C50HFGM66 SMQ320C50PQM66
Contextual Info: SMJ320C50/SMQ320C50 DIGITAL SIGNAL PROCESSOR SGUS020 – JUNE 1996 D D D D D D D D D D D D D D D D D ÉÉ ÉÉÉÉ ÉÉ ÉÉ ÉÉÉÉ ÉÉ ÉÉ ÉÉ ÉÉ ÉÉ 100 ÉÉ ÉÉ ÉÉ ÉÉ 1 99 33 66 D HFG PACKAGE TOP VIEW 132 D D Military Operating Temperature Range:

NBXDBA012

Abstract: NBXDBA012LN1TAG on-semiconductor data
Contextual Info: NBXDBA012 3.3 V, 106.25 MHz / 212.5 MHz LVPECL Clock Oscillator The NBXDBA012 dual frequency crystal oscillator XO is designed to meet today's requirements for 3.3ĂV LVPECL clock generation applications. The device uses a high Q fundamental crystal and Phase Lock Loop (PLL) multiplier to provide selectable 106.25

320C50A

Abstract: C50A SMJ320C50AGFAM40 SMJ320C50AGFAM50 SMJ320C50AHFGM40 SMJ320C50AHFGM50 RW109 C50A-50
Contextual Info: SMJ320C50A DIGITAL SIGNAL PROCESSOR SGUS018 – JANUARY 1994 • • • • • • • • • • • • • • • • • 100 ÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉ 1 99 ÉÉÉ ÉÉÉÉÉ ÉÉ ÉÉÉ ÉÉÉ ÉÉ ÉÉ 33 66 • ÉÉ ÉÉ ÉÉÉ ÉÉÉ HFG PACKAGE

AD7731BR

Abstract: C3152 opto 1230 AD7731 AD7731BN AD7731BRU EVAL-AD7731EB
Contextual Info: a Low Noise, High Throughput 24-Bit Sigma-Delta ADC AD7731 GENERAL DESCRIPTION FEATURES 24-Bit Sigma-Delta ADC 16 Bits p-p Resolution at 800 Hz Output Rate Programmable Output Rates up to 6.4 kHz Programmable Gain Front End ؎0.0015% Nonlinearity Buffered Differential Inputs

031MF

Contextual Info: PM73122 AAL1GATOR-32 PRELIMINARY STANDARD PRODUCT DATASHEET PMC-1981419 ISSUE 4 32 LINK CES/DBCES AAL1 SAR PM73122 AAL1GATOR-32 ATM ADAPTATION LAYER 1 SEGMENTATION AND REASSEMBLY PROCESSOR-32 DATASHEET PROPRIETARY AND CONFIDENTIAL PRELIMINARY ISSUE 4: JANUARY 2000

PM7366

Contextual Info: PM7366 FREEDM-8 DATA SHEET PMC-970930 ISSUE 3 FRAME ENGINE AND DATA LINK MANAGER PM7366 FREEDM -8 EIGHT CHANNEL FRAME ENGINE AND DATALINK MANAGER PROPRIETARY AND CONFIDENTIAL ISSUE 3: AUGUST 1999 PMC-Sierra, Inc. 105 - 8555 Baxter Place Burnaby, BC Canada V5A 4V7 604 .415.6000

Contextual Info: SMJ320C50KGD DIGITAL SIGNAL PROCESSOR KNOWN GOOD DIE SGZS007A - JUNE 1996 - REVISED JUNE 1997 Processed to MIL-PRF-38535 Fast Instruction Cycle Time of 30 ns, 40 ns, and 50 ns Source-Code Compatible With all ’C1x and ’C2x Devices RAM-Based Operation - 9K-Words x 16-Bit Dual-Access On-Chip

FBD25

Abstract: hesd 50 FBD15 MA6 rs232 driver jack p4 2.1mm JP21-JP24 ColdFire v5 nc10 samsung EVCC12 qd33
Contextual Info: A B C 7 18 31 42 VCC VCC VCC VCC GND GND GND GND 28 34 39 45 GND GND GND GND 4 10 15 21 +3.3 4x 4.7K 1 PP[0:7] RP6 7 5 3 1 7 5 3 1 8 6 4 2 8 6 4 2 7 18 31 42 28 34 39 45 4x 4.7K 1A1 1A2 1A3 1A4 1A5 1A6 1A7 1A8 2A1 2A2 2A3 2A4 2A5 2A6 2A7 2A8 1DIR 1OE 2OE 2DIR

h22 8-pin

Abstract: J68 10A PL-20A DC3BE J119 J1266 1J44 PL34A JITo-2-dc3 J127
Contextual Info: ORLI10G ver. 1.5 1 01/29/03 Lattice Semiconductor Corp SECTION PAGE LAYOUT OF ORLI10G BOARD: 3 CONNECTORS AND JUMPERS J1 TO J127: 4 CONNECTORS CON1 TO CON5: 18 ADJUSTABLE RESISTORS: 22 ORLI10G ver. 1.5 2 01/29/03 Lattice Semiconductor Corp Layout of ORLI10G board:

Contextual Info: LTC2209 16-Bit, 160Msps ADC FEATURES n n n n n n n n n n n n n n DESCRIPTION Sample Rate: 160Msps 77.3dBFS Noise Floor 100dB SFDR SFDR >84dB at 250MHz 1.5VP-P Input Range PGA Front End (2.25VP-P or 1.5VP-P Input Range) 700MHz Full Power Bandwidth S/H Optional Internal Dither

TMS320C50DU

Abstract: Acc 2089 mc 4069 TEXAS INSTRUMENTS, die attach datasheet and application 7217 SMJ320C50 SMJ320C50KGD
Contextual Info: SMJ320C50KGD DIGITAL SIGNAL PROCESSOR KNOWN GOOD DIE SGZS007B – JUNE 1996 – REVISED JUNE 2000 D D D D D D D D Processed to MIL-PRF-38535 Fast Instruction Cycle Time of 30 ns and 40 ns Source-Code Compatible With all ’C1x and ’C2x Devices RAM-Based Operation

Contextual Info: SM320C50ĆEP DIGITAL SIGNAL PROCESSOR SGUS040A − AUGUST 2002 − REVISED JANUARY 2006 D Controlled Baseline D D D D D D D D D D D PQ PACKAGE TOP VIEW − One Assembly/Test Site, One Fabrication Site Enhanced Diminishing Manufacturing Sources (DMS) Support

sharc ADSP-21xxx general block diagram

Abstract: panasonic ECU diagram of gunn diode schematic diagram vga to rca S3C6430 adobe cs5 tutorials pcb 2.5mm female stereo pins 3.5mm Stereo jack pinout female ADSP-21xxx PHONEJACK STEREO SW
Contextual Info: ADSP-21065L EZ-KIT Lite Evaluation System Manual Part Number: 82-000490-01 Revision 2.0 January 2003 Notice Analog Devices, Inc. reserves the right to make changes to or to discontinue any product or service identified in this publication without notice. Analog Devices assumes no liability for Analog Devices applications assistance, customer product design,

7404

Contextual Info: TMP320C50KGD, TMP320LC50KGD DIGITAL SIGNAL PROCESSOR KNOWN GOOD DIE SGZS008C – JULY 1996 – REVISED JUNE 2000 D 25-ns, 35-ns, and 50-ns Single-Cycle D D D D D D Instruction Execution Time for 5-V Operation 50-ns Single-Cycle Instruction Execution Time for 3.3-V Operation

RD13D

Contextual Info: D A TA S H E E T PM PMC-960758 ISSUE 5 PMC-Sierra,Inc. PM7364 f r e e d m -32 FRAME ENGINE AND DA TA U N K MANA GER PM7364 FREEDM -32 FRAME ENGINE AND DATALINK MANAGER DATA SHEET ISSUE 5: MAY 1998 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE

block diagram of TMS320C5X starter kit

Abstract: TMS320 DSP kit circuit diagram 84 PIN CERAMIC QUAD FLAT PACK TEXAS INSTRUMENTS pipeline TMS320C5x architecture diagram PLU processor TMDX3080005 TMDS3200051 dsp processor Architecture of TMS320C5X
Contextual Info: SMJ320C50/SMQ320C50 DIGITAL SIGNAL PROCESSOR SGUS020 – JUNE 1996 D D D D D D D D D D D D D D D D D ÉÉ ÉÉÉÉ ÉÉ ÉÉ ÉÉÉÉ ÉÉ ÉÉ ÉÉ ÉÉ ÉÉ 100 ÉÉ ÉÉ ÉÉ ÉÉ 1 99 33 66 D HFG PACKAGE TOP VIEW 132 D D Military Operating Temperature Range: