VDD14 Search Results

Contextual Info: SMJ320C50/SMQ320C50 DIGITAL SIGNAL PROCESSOR SGUS020B – JUNE 1996 – REVISED SEPTEMBER 2001 D Military Operating Temperature Range: D D D D D D D D D D D D D D D D D ÉÉ ÉÉ 100 132 ÉÉ ÉÉ 1 99 33 67 ÉÉ ÉÉ 66 D ÉÉ ÉÉ ÉÉ ÉÉ 34 D D – 55°C to 125°C

NJU6678V

Abstract: NJU6678VA NJU6678VB NJU6678VCL S102 S103 S104 S105 S130 S131
Contextual Info: NJU6678V 104 コモンx 132 セグメント ビットマップ LCD ドライバ •概 ■概 要 要 ■外 形 N J U 6 6 7 8 V は､104ｺﾓﾝ× ､104ｺﾓﾝ × 132ｾｸﾞﾒﾝﾄﾋﾞｯﾄﾏｯﾌﾟLCDﾄﾞﾗｲﾊﾞです。 132ｾｸﾞﾒﾝﾄﾋﾞｯﾄﾏｯﾌﾟLCDﾄﾞﾗｲﾊﾞ です。

Myson MTD972

Abstract: 10BASET 20MHZ MTD972 1b.9 MYSON TECHNOLOGY
Contextual Info: MTD972 Preliminary MYSON TECHNOLOGY 100BaseTX PCS/PMA FEATURES • · · · · · · · · · · IEEE 802.3 10BaseT and 802.3u 100BaseTx compliant. MII interface with serial management. Auto negotiation compatible with next page capability. 100BaseTx PCS/PMA function with on-chip clock generation and recovery.

KS0104

Abstract: KS0083 KS0103
Contextual Info: CMOS DIGITAL INTEGRATED CIRCUIT KS0104 80 CHANNEL SEGMENT DRIVER FOR LCD DOT MATRIX LCD The K S 0 1 0 4 is a LCD driver LSI w hich is fabricated b y low pow e r C M OS high voltage proce ss te ch n olo gy This device co nsists of 8 0 bit bidirectional sh ift register, 8 0 b it data latch and 8 0 b it driver

Contextual Info: SM320C50ĆEP DIGITAL SIGNAL PROCESSOR SGUS040A − AUGUST 2002 − REVISED JANUARY 2006 D Controlled Baseline D D D D D D D D D D D PQ PACKAGE TOP VIEW − One Assembly/Test Site, One Fabrication Site Enhanced Diminishing Manufacturing Sources (DMS) Support

Contextual Info: SMJ320C50/SMQ320C50 DIGITAL SIGNAL PROCESSOR SGUS020B - JUNE 1996 - REVISED SEPTEMBER 2001 D Military Operating Temperature Range: D D D D D D D D D D D D D D D D D 100 132 1 33 66 D 34 D D - 55°C to 125°C Processed to MIL-PRF-38535 Fast Instruction Cycle Time 30 ns and

Contextual Info: SM320C50ĆEP DIGITAL SIGNAL PROCESSOR SGUS040A − AUGUST 2002 − REVISED JANUARY 2006 D Controlled Baseline D D D D D D D D D D D PQ PACKAGE TOP VIEW − One Assembly/Test Site, One Fabrication Site Enhanced Diminishing Manufacturing Sources (DMS) Support

MC68HC16Z1CFC16

Abstract: 10K SIP Resistor 3FW 94 lcd 2X20 RAM 62256 80C32MOD-ULE-DIP 3FW 59 80C32 MAX147EVC16-DIP MAX147EVC32-DIP
Contextual Info: 19-4751; Rev 1; 1/97 MAX147 Evaluation System/Evaluation Kit _Component List DESIGNATION QTY DESCRIPTION C1, C7–C14 9 0.01µF ceramic capacitors C2, C4, C6, C15, C17–C20 8 0.1µF ceramic capacitors C3 C5 C16 J1 J18 JU1, JU2, JU5 R1-R8

SMJ320C50

Abstract: SMJ320C50GFAM50 SMJ320C50GFAM66 SMJ320C50HFGM50 SMJ320C50HFGM66 SMQ320C50PQM66
Contextual Info: SMJ320C50/SMQ320C50 DIGITAL SIGNAL PROCESSOR SGUS020 – JUNE 1996 D D D D D D D D D D D D D D D D D ÉÉ ÉÉÉÉ ÉÉ ÉÉ ÉÉÉÉ ÉÉ ÉÉ ÉÉ ÉÉ ÉÉ 100 ÉÉ ÉÉ ÉÉ ÉÉ 1 99 33 66 D HFG PACKAGE TOP VIEW 132 D D Military Operating Temperature Range:

320C50A

Abstract: C50A SMJ320C50AGFAM40 SMJ320C50AGFAM50 SMJ320C50AHFGM40 SMJ320C50AHFGM50 RW109 C50A-50
Contextual Info: SMJ320C50A DIGITAL SIGNAL PROCESSOR SGUS018 – JANUARY 1994 • • • • • • • • • • • • • • • • • 100 ÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉ 1 99 ÉÉÉ ÉÉÉÉÉ ÉÉ ÉÉÉ ÉÉÉ ÉÉ ÉÉ 33 66 • ÉÉ ÉÉ ÉÉÉ ÉÉÉ HFG PACKAGE

Contextual Info: UNISONIC TECHNOLOGIES CO., LTD UB261 Preliminary CMOS IC 1-CELL LITHIUM-ION/POLYMER BATTERY PROTECTION IC  DESCRIPTION 6 The UTC UB261 is a series of lithium-ion/lithium-polymer rechargeable battery protection ICs incorporating high accuracy voltage detection circuits and delay circuits.

MT48LC8M16A2

Abstract: PC15 RTL8201BL header8 DB9_MALE AT45DB128
Contextual Info: Port C Pins assignment 104 PB22/SCK1 as UART1 RI Input 122 PB27/PCK0 as UART1 DTR (Output) ADDR12 not connected to U3,U4 ADDR13 connected to U3.A11,U4.A11 See Page 139 Man.rev.from 22-Aug-03 R11 10 C27 0.1uF R14 10 C30 0.1uF R18 10 C19 0.1uF VDDPLL PLLRCA

MN103SfC2d

Abstract: MN103SFA MN103SFa5K MN103SFA7K MN103SC2A MN103SA5K PX-ICE-103SA5 DOG 62 D3 MN103SF MN103SfA7
Contextual Info: AM3 MN103/MN103S Series AM3 (MN103/MN103S) Series The AM3 series are the 32-bit microcomputer suitable for multimedia applications such as movie, digital audio, graphic and communications. Both high quality and low power consumption have been achieved through use of the C language architecture and optimized C compiler.

031MF

Contextual Info: PM73122 AAL1GATOR-32 PRELIMINARY STANDARD PRODUCT DATASHEET PMC-1981419 ISSUE 4 32 LINK CES/DBCES AAL1 SAR PM73122 AAL1GATOR-32 ATM ADAPTATION LAYER 1 SEGMENTATION AND REASSEMBLY PROCESSOR-32 DATASHEET PROPRIETARY AND CONFIDENTIAL PRELIMINARY ISSUE 4: JANUARY 2000

MIL I 23659

Abstract: 42058
Contextual Info: TMP320C50KGD, TMP320BC51KGD DIGITAL SIGNAL PROCESSOR KNOWN GOOD DIE S G ZS 008-JU LY 1996 • F as t Instr uct i on Cy c l e T i me s of 35 ns and SO ns • S o u r c e - C o d e C o m p a t i b l e With all ’C 1 x and ’C2 x D e v i c e s • 1 6- Bi t Parall el L ogi c Uni t P L U

Contextual Info: SMJ320C50KGD DIGITAL SIGNAL PROCESSOR KNOWN GOOD DIE SGZS007A - JUNE 1996 - REVISED JUNE 1997 Processed to MIL-PRF-38535 Fast Instruction Cycle Time of 30 ns, 40 ns, and 50 ns Source-Code Compatible With all ’C1x and ’C2x Devices RAM-Based Operation - 9K-Words x 16-Bit Dual-Access On-Chip

FBD25

Abstract: hesd 50 FBD15 MA6 rs232 driver jack p4 2.1mm JP21-JP24 ColdFire v5 nc10 samsung EVCC12 qd33
Contextual Info: A B C 7 18 31 42 VCC VCC VCC VCC GND GND GND GND 28 34 39 45 GND GND GND GND 4 10 15 21 +3.3 4x 4.7K 1 PP[0:7] RP6 7 5 3 1 7 5 3 1 8 6 4 2 8 6 4 2 7 18 31 42 28 34 39 45 4x 4.7K 1A1 1A2 1A3 1A4 1A5 1A6 1A7 1A8 2A1 2A2 2A3 2A4 2A5 2A6 2A7 2A8 1DIR 1OE 2OE 2DIR

99S100

Abstract: A 2497 SS131 W NJU6678V NJU6678VA NJU6678VB NJU6678VCL S102 S103 S104
Contextual Info: NJU6678V 暫定資料 104 コモンx 132 セグメント ビットマップ LCD ドライバ •概 要 ■概 要 ■外 形 N J U 6 6 7 8 V は､104ｺﾓﾝ ､104ｺﾓﾝ× × 132ｾｸﾞﾒﾝﾄﾋﾞｯﾄﾏｯﾌﾟLCDﾄﾞﾗｲﾊﾞ

MSM6794

Abstract: ic 4058 DATASHEET 4058 PEDL6794-03 PEDL6794-04 CO 4058
Contextual Info: PEDL6794-04 PEDL6794-03 el Pr im DOT MATRIX LCD DRIVER WITH 128-CHANNEL RAM GENERAL DESCRIPTION The MSM6794 is a dot matrix graphic liquid crystal display LSI device to display bit maps. It drives an LCD panel for dot matrix graphic display under the control of a 4- or 8-bit

TA 7698 AP

Contextual Info: PRELIMINARY INFORMATION L9D3256M32SBG1 L9D3512M32SBG1 8-16 Gb, DDR3, 256-512M x 32 Single Channel Memory Module Benefits FEATURES " " " " " " Configuration: "‚"N;F5478O54UDI3<"54Ogi"z"54"z" 8 banks ‚"N;F5734O54UDI3<"86Ogi"z"54"z" 8 banks DDR3 Integrated Module [iMOD]:

prng

Abstract: 77V106 IDT77V106 IDT77V106L25 PE-67583 TLA-6M103
Contextual Info: IDT77V106L25 3.3V ATM PHY for 25.6 and 51.2 Mbps Features ! ! ! ! ! ! ! ! ! ! ! ! ! Description Performs the PHY-Transmission Convergence TC and Physical Media Dependent (PMD) Sublayer functions of the Physical Layer Compliant to ATM Forum (af-phy-040.000) and ITU-T I.432.5

ana60

Abstract: AFM2 AFM8 hdlc INTEL 386EX TDA 1512 STLC5466 TQFP176 Motorola CMOS Dynamic RAM 1M x 1 1989
Contextual Info: STLC5466 64 CHANNEL-MULTI HDLC WITH N X 64KB/S SWITCHING MATRIX ASSOCIATED • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ 64 TX HDLCs with broadcasting capability and/ or CSMA/CR function with automatic restart in case of Tx frame abort

TMS320C50DU

Abstract: Acc 2089 mc 4069 TEXAS INSTRUMENTS, die attach datasheet and application 7217 SMJ320C50 SMJ320C50KGD
Contextual Info: SMJ320C50KGD DIGITAL SIGNAL PROCESSOR KNOWN GOOD DIE SGZS007B – JUNE 1996 – REVISED JUNE 2000 D D D D D D D D Processed to MIL-PRF-38535 Fast Instruction Cycle Time of 30 ns and 40 ns Source-Code Compatible With all ’C1x and ’C2x Devices RAM-Based Operation

Contextual Info: SM320C50ĆEP DIGITAL SIGNAL PROCESSOR SGUS040A − AUGUST 2002 − REVISED JANUARY 2006 D Controlled Baseline D D D D D D D D D D D PQ PACKAGE TOP VIEW − One Assembly/Test Site, One Fabrication Site Enhanced Diminishing Manufacturing Sources (DMS) Support