VCXO 2420 Search Results

1965MHz

Abstract: VCXO 27MHZ 2052M 3.3v
Contextual Info: XO & VCXO Product Selector Guide Output type Multiplication Input Range Output Frequency 1MHz 12-27MHz 1x Sub 1pS CMOS Selectable Multiplier 1x (Sub 1pS) PECL LVDS Fixed Multiplier Selectable Multiplier CMOS 100 0027B 0251 65-130MHz Selectable Multiplier

Contextual Info: CY24207 MediaClock PDP Clock Generator Features Benefits • Integrated phase-locked loop Internal PLL with up to 400-MHz internal operation • Low jitter, high accuracy outputs Meets critical timing requirements in complex system designs • VCXO with Analog Adjust

vco 27MHz

Abstract: CY24204 CY24204ZC-3
Contextual Info: CY24204 MediaClock DTV, STB Clock Generator Features Benefits • Integrated phase-locked loop PLL Internal PLL with up to 400-MHz internal operation • Low jitter, high-accuracy outputs Meets critical timing requirements in complex system designs • VCXO with Analog Adjust

CY24207

Abstract: CY24207ZC-1 CY24207ZC-1T CY24207ZC-2 CY24207ZC-2T
Contextual Info: CY24207 MediaClock PDP Clock Generator Features • • • • Benefits Integrated phase-locked loop PLL Low-jitter, high-accuracy outputs VCXO with Analog Adjust 3.3V operation • Internal PLL with up to 400-MHz internal operation • Meets critical timing requirements in complex system

27MHZ crystal

Abstract: 74250 CY24204
Contextual Info: CY24204 MediaClock DTV, STB Clock Generator Features • • • • Benefits Integrated phase-locked loop PLL Low jitter, high-accuracy outputs VCXO with Analog Adjust 3.3V operation • Internal PLL with up to 400MHz internal operation • Meets critical timing requirements in complex system

CY24207

Abstract: CY24207ZC-1 CY24207ZC-1T CY24207ZC-2 CY24207ZC-2T
Contextual Info: CY24207 MediaClock PDP Clock Generator Features • • • • Benefits Integrated phase-locked loop PLL Low-jitter, high-accuracy outputs VCXO with Analog Adjust 3.3V operation • Internal PLL with up to 400-MHz internal operation • Meets critical timing requirements in complex system

74250

Contextual Info: CY24204 MediaClock DTV, STB Clock Generator Features Benefits • Integrated phase-locked loop PLL • Internal PLL with up to 400-MHz internal operation • Low jitter, high-accuracy outputs • Meets critical timing requirements in complex system designs

74250

Abstract: CY24204 CY24204ZC-3 CY24204ZC-3T CY24204ZC-4 rate fxo 020
Contextual Info: CY24204 MediaClock DTV, STB Clock Generator Features Benefits • Integrated phase-locked loop PLL • Internal PLL with up to 400-MHz internal operation • Low jitter, high-accuracy outputs • Meets critical timing requirements in complex system designs

ZZ16

Abstract: cut template DRAWING CY24204 CY24204ZXC-3
Contextual Info: CY24204 MediaClock DTV, STB Clock Generator Features Benefits • Integrated phase-locked loop PLL ■ Internal PLL with up to 400-MHz internal operation ■ Low jitter, high-accuracy outputs ■ Meets critical timing requirements in complex system designs

Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA M C 1648 V oltage C ontrolled O scillato r Consider MC12148 for New Designs The MC1648 requires an external parallel tank circuit consisting of the inductor L and capacitor (C). For Maximum Performance Q l £ 100 at

MC1648

Abstract: BR504 variable inductor values for 10MHz- 100MHz oscillator HP5210A MC1648 internal schematic MC12148 ETAS Capacitance Varactor Diode KV MC68836 1200 ohm RESISTOR
Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA M C1648 V oltage Controlled O scillator Consider MC12148 for New Designs The MC1648 requires an external parallel tank circuit consisting of the inductor L and capacitor (C). For Maximum Performance Q l > 100 at Frequency of Operation.

Contextual Info: 3.3V PECL/ECL DIFFERENTIAL PHASE-FREQUENCY DETECTOR FEATURES SY100EP140L DESCRIPTION • ■ ■ ■ ■ ■ >2GHz maximum frequency < 220ps rise/fall time Low-voltage: +3.3V ±10% operation Wide operating temperature range: –40°C to +85°C Fully differential throughput architecture

fb 1225

Abstract: SY100EP140L SY100EP140LZI SY100EP140LZITR
Contextual Info: 3.3V PECL/ECL DIFFERENTIAL PHASE-FREQUENCY DETECTOR FEATURES SY100EP140L FINAL DESCRIPTION • ■ ■ ■ ■ ■ >2GHz maximum frequency < 220ps rise/fall time Low-voltage: +3.3V ±10% operation Wide operating temperature range: –40°C to +85°C Fully differential throughput architecture

Contextual Info: 3.3V PECL/ECL DIFFERENTIAL PHASE-FREQUENCY DETECTOR SY100EP140L FINAL FEATURES • ■ ■ ■ ■ ■ >2GHz maximum frequency < 220ps rise/fall time Low-voltage: +3.3V ±10% operation Wide operating temperature range: –40°C to +85°C Fully differential throughput architecture

TR 1225

Abstract: SY100EP140L SY100EP140LZC SY100EP140LZCTR SY100EP140LZI SY100EP140LZITR that 2155
Contextual Info: Precision Edge PrecisionSY100EP140L Edge™ 3.3V PECL/ECL DIFFERENTIAL SY100EP140L PHASE-FREQUENCY DETECTOR FINAL Micrel FEATURES • ■ ■ ■ ■ ■ >2GHz maximum frequency < 220ps rise/fall time Low-voltage: +3.3V ±10% operation Wide operating temperature range: –40°C to +85°C

SY100EP140L

Abstract: SY100EP140LZC SY100EP140LZCTR SY100EP140LZI SY100EP140LZITR SY100EP140LZG
Contextual Info: Micrel, Inc. 3.3V PECL/ECL DIFFERENTIAL PHASE-FREQUENCY DETECTOR Precision Edge SY100EP140L Precision Edge® SY100EP140L FEATURES • ■ ■ ■ ■ ■ >2GHz maximum frequency < 220ps rise/fall time Low-voltage: +3.3V ±10% operation Wide operating temperature range: –40°C to +85°C

Contextual Info: Micrel, Inc. 3.3V PECL/ECL DIFFERENTIAL PHASE-FREQUENCY DETECTOR Precision Edge SY100EP140L Precision Edge® SY100EP140L FEATURES • ■ ■ ■ ■ ■ >2GHz maximum frequency < 220ps rise/fall time Low-voltage: +3.3V ±10% operation Wide operating temperature range: –40°C to +85°C

485G

Abstract: AND8020 NBLVEP16VR NBLVEP16VRMN NBLVEP16VRMNR2 NBWLVEP16VR
Contextual Info: NBLVEP16VR 2.5V/3.3V/5V ECL Differential Receiver/Driver with Oscillator Gain Stage and Enabled High Gain Outputs The NBLVEP16VR is an ECL/LVPECL oscillator gain stage with high−gain output buffers, selectable output enable and a feedback buffer. The NBLVEP16VR is a solution for crystal oscillators and

Contextual Info: NBLVEP16VR 2.5V/3.3V/5V ECL Differential Receiver/Driver with Oscillator Gain Stage and Enabled High Gain Outputs The NBLVEP16VR is an ECL/LVPECL oscillator gain stage with high−gain output buffers, selectable output enable and a feedback buffer. The NBLVEP16VR is a solution for crystal oscillators and

Contextual Info: This document, NBLVEP16VR/D has been canceled. 01/APR/2005 Per PAUL LEE Semiconductor Components Industries, LLC, 2006 June, 2006 − Rev. 4 1 Publication Order Number: NBLVEP16VR/D NBLVEP16VR NBLVEP16VR XXXX ,

tms3200m642

Abstract: tms320dm270 TNETW1130 DM270 tms320dsc DSP TMS320DM270 AM 5766 analog DVB smart card rs232 iris convert hdtv decoder to modem for browsing "full hd" mobile phone camera pinout
Contextual Info: R E A L W O R L D S P I G N A L TM R O C E S S I N G Video and Imaging Solutions Guide Amplifiers, Audio/Video Codecs, Clock Distribution, Data Converters, Digital Light Processing , Digital Media Processors, Digital Signal Processors, Interface, Logic,

ssf 7509 equivalent

Abstract: lt 747B PM 8058 SMD code 307C interfacing 8279 to the 8086 mac 87A6 TA 7176 IC smd cross reference msd 702F MSD 7818 S19208CBI
Contextual Info: S19208CBI Niagara Datasheet Revision 1.11 January 16, 2003 AMCC - PROPRIETARY AND CONFIDENTIAL RESTRICTED DISTRIBUTION NDA REQUIRED AMCC Dear customer, Thank you for choosing an AMCC device. We appreciate your confidence in our products. To ensure your complete satisfaction with our products and technologies, we have prepared this

TMS320C64xx

Abstract: 6713 SPRU266 SPRU401J pulse code interval encoding using c6713 pulse code interval encoding using c6713 timer 458 TIMER CIRCUIT COLLECTION B536 rld bh-16 SPRU401 TMS320C64xx cpu
Contextual Info: TMS320C6000 Chip Support Library API Reference Guide Literature Number SPRU401J August 2004 Printed on Recycled Paper IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries TI reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any

SY 351/6

Abstract: HP8656B service manual PWB 826 service manual PS 224 CITS25 DXSN2112 pj 939 PS-224 2 X 2 DUAL CROSSPOINT SWITCH amcc 10G palce programming algorithm
Contextual Info: SERDES Handbook April 2003 Dear Valued Customer, Lattice Semiconductor is pleased to provide you this second edition of our SERDES Handbook. Since offering the initial version last year, we have introduced several new products based on our superior sysHSI technology: