VCO PLL Search Results

ADF4350

Abstract: ADF4351 ADF4350BCPZ ADF4350BCPZ-RL7 SW 5189 C EVAL-ADF4350EB2Z ADSP-BF527 DB31 E5052A GSM900
Contextual Info: Wideband Synthesizer with Integrated VCO ADF4350 FEATURES GENERAL DESCRIPTION Output frequency range: 137.5 MHz to 4400 MHz Fractional-N synthesizer and integer-N synthesizer Low phase noise VCO Programmable divide-by-1/-2/-4/-8/-16 output Typical rms jitter: <0.4 ps rms

Contextual Info: TH72005 315MHz FSK/ASK Transmitter Features ! ! ! ! ! ! ! ! Fully integrated PLL-stabilized VCO Frequency range from 290 MHz to 350 MHz Single-ended RF output FSK through crystal pulling allows modulation from DC to 40 kbit/s High FSK deviation possible for wideband data

TRF1015

Contextual Info: TRF1015 CELLULAR RECEIVER FRONT-END ^ • • • • • • • • • - JUNE 1996 Low-Noise Amplifier LNA , Radio Frequency (RF) Mixer, and Voltage-Controlled Oscillator (VCO) High 1-dB Compression Mode

DSN-3019A-119

Contextual Info: DSN-3019A-119+ Frequency Synthesizer Typical Performance Data FREQ. POWER OUTPUT HARMONICS VCO CURRENT PLL CURENT dBm (dBc) (mA) (mA) (MHz) 1788 1888 2016 2144 2272 2400 2528 2656 2784 2912 3019 -45ºC +25ºC +85ºC -45ºC F2 +25ºC 1.00 1.60 1.78 2.15 2.54

Contextual Info: ICS2694 Integrated Circuit Systems, Inc. Motherboard Clock Generator Features Applications • Low cost - eliminates multiple oscillators and Count Down Logic • CPU clock and Co-processor clock • Hard Disk and Floppy Disk clock Primary VCO has 16 Mask Programmable frequencies

7-segment 4 digit 5461

Abstract: TLR-321 TLR321 cd 5411 ic tc9109 TC9109BP
Contextual Info: TENTATIVE Unit in mm . 10 18 TC9109BP CB TRANSCEIVER PLL FREQUENCY SYNTHESIZER r u u u u u u u u 22.8 M A X • TC9109BP C-MOS LSI may be used a 40 7.62±Q25 channels CB transceiver frequency synthesizer. - • Included high speed programmable counter, operated direct division of VCO can be

Contextual Info: TLC2933 HIGH-PERFORMANCE PHASE-LOCKED LOOP SLAS136B – APRIL 1996 – REVISED JANUARY 2002 D D D D D D D Voltage-Controlled Oscillator VCO Section: – Ring Oscillator Using Only One External Bias Resistor (RBIAS) – Lock Frequency: 43 MHz to 100 MHz (VDD = 5 V ±5%,

TLC2933

Abstract: TLC2933IPW TLC2933IPWG4 TLC2933IPWLE TLC2933IPWR TLC2933IPWRG4
Contextual Info: TLC2933 HIGHĆPERFORMANCE PHASEĆLOCKED LOOP SLAS136B − APRIL 1996 − REVISED JANUARY 2002 D Voltage-Controlled Oscillator VCO D D D D D D Section: − Ring Oscillator Using Only One External Bias Resistor (RBIAS) − Lock Frequency: 43 MHz to 100 MHz (VDD = 5 V ±5%,

LTC3300

Abstract: LTspice DIODE ZENER 3.1V 250mW LTC3105 supercapacitor spice balancing circuit for supercapacitor thermoelectric generator model reports LTM8047 ltc4425 Sanyo supercapacitors
Contextual Info: January 2012 I N T H I S I S S U E integer-N synthesizer with integrated VCO in a 4mm x 5mm package 9 supercapacitor-based power supply ride-through system 15 ultralow-EMI, µModule Volume 21 Number 4 Dual Output DC/DC Controller Combines Digital Power System

AN1091

Abstract: DL140 MPC930 MPC931 Nippon capacitors
Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA Low Voltage PLL Clock Driver MPC930 MPC931 The MPC930/931 is a 3.3V compatible, PLL based clock driver device targeted for high performance clock applications. With output frequencies of up to 150MHz and output skews of 300ps the MPC930/931 is ideal for

Contextual Info: ICS1574 Integrated Circuit Systems, Inc. User Programmable Laser Engine Pixel Clock Generator Description Features The ICS1574 is a very high performance monolithic phaselocked loop PLL frequency synthesizer designed for laser engine applications. Utilizing ICS’s advanced CMOS mixed­

Contextual Info: Quality Semiconductor, I nc. QS5940 SuperSync PCI Controller PLL Clock Driver PRELIMINARY FEATURES/BENEFITS DESCRIPTION • • • • • • • • • • • QS5940 is a high-performance, low skew, low jitter phase-locked loop PLL clock driver. Two banks of

Contextual Info: QS5LV931 ADVANCE INFORMATION 3.3V Low Skew CMOS PLL Clock Driver With Integrated Loop Filter Q u a l it y S e m ic o n d u c t o r , I n c . DESCRIPTION FEATURES/BENEFITS JEDEC LVTTL compatible level Clock input is 5V tolerant Q outputs, Q/2 output < 300ps output skew, Q0-Q4

TA76494

Abstract: TC9192 TA8443 QFP60 TA8444F TA8443F TA8444 pll motor control fg fv sta 515 vh va77
Contextual Info: TA8444F PRELIMINARY DATA DOUBLE PLL-PWM 3-PHASE HALL MOTOR PRE-DRIVER TA844F is 3-phase hall motor pre-driver with PLL controller and PWM controller. 8 bit D/A converter system has been employed for each of the speed control system AFC and the phase control system (APC).

100MHZ

Abstract: PLL2109X digital pll 500MHz
Contextual Info: 100MHZ ~ 500MHZ FSPLL PLL2109X PRELIMINARY GENERAL DESCRIPTION The pll2109x is a Phase Locked Loop(PLL) frequency synthesizer. The PLL provides frequency multiplication capabilities. Its output clock frequency FOUT is related to the input clock frequency FIN by the following

Contextual Info: HD155008T Built-in 1.1 GHz / 460 MHz High Speed Prescaler Dual PLL Frequency Synthesizer IC HITACHI ADE-207-239 Z Preliminary, 1st. Edition November 1997 Description The HD155008T is a dual PLL frequency synthesizer IC that was developed for mobile telecommunication

7227 up down counter

Abstract: phase detector and up down counter
Contextual Info: Product Specification PE3240 2.2 GHz UltraCMOS Integer-N PLL for Low Phase Noise Applications Product Description Peregrine’s PE3240 is a high performance integer-N PLL capable of frequency synthesis up to 2.2 GHz. The superior phase noise performance of the PE3240 is ideal

Contextual Info: AV9173-15 Integrated Circuit Systems, Inc. Video Genlock PLL General Description Features The AV9173-15 provides the analog circuit blocks required for implementing a video genlock dot pixel clock generator. It contains a phase detector, charge pump, loop

Contextual Info: AV9173-01 Integrated Circuit Systems, Inc. Video Genlock PLL General Description Features The AV9173-01 provides the analog circuit blocks required for im plem enting a video genlock dot pixel clock generator. It contains a phase detector, charge pump, loop

B38 zener data

Contextual Info: ICS2595 Integrated Circuit Systems, Inc. Advance Information User-Program m able Dual H igh-Perform ance Clock Generator Description Features The ICS2S95 is a dual-PLL phase-locked loop clock gener­ ator specifically designed for high-resolution, high-refresh

Contextual Info: SY89538L 3.3V Precision LVPECL and LVDS Programmable Multiple Output Bank Clock Synthesizer and Fanout Buffer with Zero Delay General Description The SY89538L integrated programmable clock synthesizer and fanout is part of a precision PLLbased clock generation family optimized for

Contextual Info: xr XRK39351 PRELIMINARY 3.3V OR 2.5V, 9-OUTPUT PLL CLOCK DRIVER AUGUST 2006 REV. P1.0.1 GENERAL DESCRIPTION input is pulled low. This is a test mode intended for system debug purposes. The XRK39351 is a low voltage PLL based clock driver designed for high speed clock distribution

rfid Rc 522

Contextual Info: LMX2354 LMX2354 PLLatinum Fractional N RF/ Integer N IF Dual Low Power Frequency Synthesizer LMX2354 2.5 GHz/550 MHz Literature Number: SNAS118B LMX2354 PLLatinum Fractional N RF/ Integer N IF Dual Low Power Frequency Synthesizer LMX2354 2.5 GHz/550 MHz General Description

Q3236

Abstract: PE9601 PE9601EK 9601-11 96011
Contextual Info: Product Specification PE9601 2200 MHz UltraCMOS Integer-N PLL for Rad Hard Applications Product Description Peregrine’s PE9601 is a high performance integer-N PLL capable of frequency synthesis up to 2200 MHz. The device is designed for superior phase noise performance while