VC48 Search Results

MC 4011 BCP

Abstract: PKT 4113 API ncp 6131 SWITCHING SYSTEMS INTERNATIONAL sqm 225 leach 1522 her 4541 MSP SNCP t 1451 n 52 toh SWITCHING SYSTEMS INTERNATIONAL sqm 350 k2400 EQUIVALENT
Contextual Info: EtherPHAST -24 Device 2x OC-12/STM-4 SONET/SDH Ethernet Mapper TXC-06745 DATA SHEET TXC-06745-MB, Ed. 2 February 2006 FEATURES APPLICATIONS • Client Interfaces: 2x GMII/24x SMII/4x TBI/MPI 24 channel packet all pin shared • Two serial Gigabit Ethernet (1.25 Gbit/s) ports with integrated CRSU/SerDes (8B/10B)

4A256

Abstract: MACH4A I1017 4a32
Contextual Info: ADVANCE INFORMATION VANTI S BEYO N D PERFO RM ANCE MACH 4A CPLD Family High Performance EE CMOS Programmable Logic With Maximum Ease Of Use DISTINCTIVE CHARACTERISTICS Features ♦ High-performance, EE CMOS 3.3-V CPLD Family ♦ Flexible architecture for rapid logic designs

Contextual Info: FINAL COM’L : -7/10/12/15 IN D :-10/12/14/18 MACH 4-64/MACH4LV-64 B E Y O N D P E R FO R M A N C E High-Performance EE CMOS Programmable Logic DISTINCTIVE CHARACTERISTICS ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ 44 pins in PLCC, 44 and 48 pins in TQFP

O2-A2

Abstract: Lattice Mach OX2 VCCIO11 ispMACH M4A3 M4A5-192 application note PAL 007 O64i
Contextual Info: ispMACH 4A CPLD Family High Performance E2CMOS In-System Programmable Logic FEATURES ◆ High-performance, E2CMOS 3.3-V & 5-V CPLD families ◆ Flexible architecture for rapid logic designs ◆ ◆ ◆ ◆ ◆ ◆ ◆ — Excellent First-Time-FitTM and refit feature

CXO 049

Abstract: GX6101 CXO 043 BX61 CI043 CXO 046 ci pal 014 V/ci pal 014
Contextual Info: MACH 4 CPLD Family BEYOND PERFO R M A N CE High Performance EE CMOS Programmable Logic FEATURES ♦ High-performance, EE CMOS 3.3-V & 5-V CPLD families ♦ Flexible architecture for rapid logic designs — Excellent First-Tim e-Fit and refit feature — SpeedLocking™ performance for guaranteed fixed timing

Contextual Info: Agilent Technologies OmniBER OTN Jitter Analyzer J7231B Technical Data Sheet Accurate, repeatable jitter measurements for SONET/SDH/OTN interfaces. OmniBER OTN Jitter Key Features • Fully complies and exceeds the requirements of ITU-T O.172 for SONET/SDH Jitter generation &

Contextual Info: ispMACH 4A CPLD Family High Performance E2CMOS In-System Programmable Logic FEATURES ◆ High-performance, E2CMOS 3.3-V & 5-V CPLD families ◆ Flexible architecture for rapid logic designs ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ — Excellent First-Time-FitTM and refit feature

O2-A2

Abstract: C10C8
Contextual Info: ispMACH 4A CPLD Family High Performance E2CMOS In-System Programmable Logic FEATURES ◆ High-performance, E2CMOS 3.3-V & 5-V CPLD families ◆ Flexible architecture for rapid logic designs ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ — Excellent First-Time-FitTM and refit feature

SDH 209

Abstract: VC4-16c BELLCORE CY7C9537B CYS25G0101DX OC48 concatenated and OC-3 and STM-1 G-783 National Standards Institute T1X15
Contextual Info: CY7C9537B CONFIDENTIAL OC-48/STM-16 Framer–POSIC2G Features • OC-48/STS-48/STM-16, OC-12/STS-12/STM-4, OC-3/STS3/STM-1 rates, concatenated and non-concatenated — Complies with ITU-Standards G.707/Y.1322 and G.783[1,2] — Complies with Bellcore GR253 rev.1, 1997[3]

T1X15

Abstract: CY7C9536B CYS25G0101DX OIF-SPI3-01 TRS-X
Contextual Info: CONFIDENTIAL CY7C9536B OC-48/STM-16 Framer with VC - POSIC2GVC Features • OC-48/STS-48/STM-16, OC-12/STS-12/STM-4, OC-3/STS3/STM-1 rates, concatenated and non-concatenated • Complies with ITU-Standards G.707/Y.1322 and G.783[1,2] • Complies with Bellcore GR253 rev.1, 1997

amcc volta

Contextual Info: S4814PBI21 Volta 48 FINAL Datasheet Revision 1.13 November 21, 2005 AMCC - PROPRIETARY AND CONFIDENTIAL RESTRICTED DISTRIBUTION NDA REQUIRED Disclaimer: AMCC is providing information within this data sheet relating to LCAS mode in which a customer may choose to operate the Volta. The data set forth

PAL 007 E

Abstract: PAL 007 B PAL 007 c PAL 007 led matrix circuits M4-256/128 pal 005 am PAL 007 A O5M12 m4lv-256/128
Contextual Info: MACH 4 CPLD Family High Performance E2CMOS In-System Programmable Logic FEATURES ◆ High-performance, E2CMOS 3.3-V & 5-V CPLD families ◆ Flexible architecture for rapid logic designs ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ — Excellent First-Time-FitTM and refit feature

PAL 007 c

Abstract: PAL 007 B PAL 007 A PAL 007 E led matrix circuits M4-256/128 grid tie inverters circuit diagrams JI 32 mach schematic O2-A2
Contextual Info: MACH 4 CPLD Family I MAC nclude s H Adv anc 4A Fam e In form ily atio n High Performance EE CMOS Programmable Logic FEATURES ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ — Excellent First-Time-FitTM and refit — SpeedLockingTM for guaranteed fixed timing — Central, input and output switch matrices for 100% routability and 100% pin-out retention

512256

Contextual Info: ispMACH 4A CPLD Family High Performance E2CMOS In-System Programmable Logic FEATURES ◆ High-performance, E2CMOS 3.3-V & 5-V CPLD families ◆ Flexible architecture for rapid logic designs ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ — Excellent First-Time-FitTM and refit feature

IGO tv circuit diagram

Abstract: 412hs
Contextual Info: FINAL COM'L: -7/10/12/15 IND: -10/12/14/18 MACH 4-64/MACH4LV-64 BEYON D PER FO R M A N C E High-Performance EE CMOS Programmable Logic DISTINCTIVE CHARACTERISTICS ♦ ♦ ♦ ♦ ♦ ♦ 44 pins in PLCC, 44 and 48 pins in TQFP 64 macroceils 7.5 ns tpQ Commercial, 10 ns tpD Industrial

Contextual Info: FINAL BEYOND PERFORMANCE COM'L: -7/10/12/15 IND: -10/12/14/18 MACH 4-32/MACH4LV-32 High-Performance EE CMOS Programmable Logic DISTINCTIVE CHARACTERISTICS ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ 44 pins in PLCC, 44 and 48 pins in TQFP 32 macrocells 7.5 ns tPD Commercial, 10 ns tPD Industrial

Contextual Info: OmniBER OTN 10G J7230A communications performance analyzer Technical specifications Effective 1st March 2003 G.709 Table of Contents Introduction . 4

393 EZ 952

Abstract: 5K432 m4as 12864j n1085 049G1 Programming mach 130
Contextual Info: D "V High Performance EE CMOS Programmable Logic FEATURES ♦ High-performance, EE CMOS 3.3-V & 5-V CPLD families ♦ Flexible architecture for rapid logic designs — Excellent First-Time-Fit and refit — SpeedLocking™ for guaranteed fixed timing — Central, input and output switch matrices for 100% routability and 100% pin-out retention

Contextual Info: ispMACH 4A CPLD Family High Performance E2CMOS In-System Programmable Logic FEATURES ◆ High-performance, E2CMOS 3.3-V & 5-V CPLD families ◆ Flexible architecture for rapid logic designs ◆ ◆ ◆ ◆ ◆ ◆ — Excellent First-Time-FitTM and refit feature

M4A3-256

Contextual Info: ispMACH 4A CPLD Family High Performance E2CMOS In-System Programmable Logic FEATURES ◆ High-performance, E2CMOS 3.3-V & 5-V CPLD families ◆ Flexible architecture for rapid logic designs ◆ ◆ ◆ ◆ ◆ ◆ — Excellent First-Time-FitTM and refit feature

CY7C9538

Abstract: CYS25G0101DX cypress 1994 sram zero concatenated and OC-3 and STM-1 3C6V 1xVC4-16c T1X15
Contextual Info: CONFIDENTIAL CY7C9538 OC-48/STM-16 Framer with Reconfigurable VC–POSIC2GVC-R Features • OC-48/STS-48/STM-16, OC-12/STS-12/STM-4, OC-3/STS3/STM-1 rates, concatenated and non-concatenated • Programmable frame tagging engine for packet preclassification enables such features as

S19225PBI22

Abstract: S19225PBI AMCC Virtual Concatenation deskew SRAM SAMSUNG
Contextual Info: S19225PBI22 Volta 192 Datasheet Revision 1.14 February 23, 2006 AMCC - PROPRIETARY AND CONFIDENTIAL RESTRICTED DISTRIBUTION NDA REQUIRED Disclaimer: AMCC is providing information within this data sheet relating to LCAS mode in which a customer may choose to operate the Volta. The data set forth

tea 1601 t

Abstract: tea 1601 O2-A2 160 e7 led matrix circuits ISPMACH ispMACH 4A Family PAL 007 PAL 007 A PAL 007 B
Contextual Info: ispMACH 4A CPLD Family High Performance E2CMOS In-System Programmable Logic FEATURES ◆ High-performance, E2CMOS 3.3-V & 5-V CPLD families ◆ Flexible architecture for rapid logic designs ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ — Excellent First-Time-FitTM and refit feature

diode K1V 452

Abstract: 09CCH 09E0H 09A1H 0943H 09C8 0951H 05C1H 1488h K1V 40 N
Contextual Info: SPECTRA-2488 Telecom Standard Product Data Sheet Released PM5315 SPECTRA-2488 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER FOR 2488 MBIT/S Data Sheet Proprietary and Confidential Released Issue 4: November, 2001 Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use