UP 6000 Search Results

GI355

Abstract: GI356 141-003 Servo servo track
Contextual Info: Incremental Encoder Resolution up to 6000 pulses GI355, GI356 Features – Standard encoder with 58 mm dia. – Speed up to 10000 rpm – Resolution up to 6000 pulses/revolution – Signal outputs A, A inv., B, B inv., N, N inv. – Temperature range at 5 VDC up to 100 °C

Contextual Info: Æ tctel - w ACT 1 Series FPGAs Features • 5V and 3.3V Families fully compatible with JEDEC specifications • Up to 2000 Gate Array Gates 6000 PLD equivalent gates • Replaces up to 50 TTL Packages • Replaces up to twenty 20-Pin PAL Packages

RD212

Abstract: A1415 A1425 A1425A-3 A1440 A1460 actcl AH25A-3
Contextual Info: Accelerator Series FPGAs - ACT 3 Family Features Replaces up to twenty 32 macro-cell CPLDs • Up to 10,000 Gate Array Equivalent Gates up to 25,000 equivalent PLD Gates Replaces up to one hundred 20-pin PAL Packages Up to 1153 Dedicated Flip-Flops

Contextual Info: Incremental encoders Shaft and lange in inch dimensions Resolution 5.6000 pulses G25 Features – Robust design with protection up to IP 67 – Shaft loading up to 150 lbs 670 N – Shock resistant up to 100 g’s – Wide temperature range -40…+100 °C

32 Bit loadable counter

Abstract: ACT 3 accelerator FPGAs Actel Accelerator fpga datasheet DLM8 A1415 A1425 A1425A-3 A1440 A1460 175-PIN
Contextual Info: Accelerator Series FPGAs – ACT 3 Family Features • Replaces up to twenty 32 macro-cell CPLDs • Up to 10,000 Gate Array Equivalent Gates up to 25,000 equivalent PLD Gates • Replaces up to one hundred 20-pin PAL Packages • Up to 1153 Dedicated Flip-Flops

Contextual Info: BACK Accelerator Series FPGAs – ACT 3 Family Features • Replaces up to twenty 32 macro-cell CPLDs • Up to 10,000 Gate Array Equivalent Gates up to 25,000 equivalent PLD Gates • Replaces up to one hundred 20-pin PAL Packages • Up to 1153 Dedicated Flip-Flops

fp1 PLC programming

Abstract: transistor A02a "alu 4 bit"
Contextual Info: NEW! -3 S p e e d s ACT" 1 Field Programmable Gate Arrays Features • Up to 2000 Gate Array Gates 6000 PLD equivalent gates • Replaces up to 50 TTL Packages • Replaces up to twenty 20-Pin PAL Packages • Design Library with over 250 Macro Functions

8 bit multiplier using vhdl code

Abstract: ado1 "Single-Port RAM"
Contextual Info: Designing ispLSI 6000 Devices in the Synplicity Environment ® 2. c4r4pl: four counters up/down, 8/16 bits, parallel load are configured as a 16-bit counter, default is up. Counter sizes can be independently changed to 8 or 16 bits for each bank; default is 16-bit. Once up, down

vhdl code for parallel to serial shift register

Abstract: isplsi architecture
Contextual Info: Designing ispLSI 6000 Devices in the Synplicity Environment ® 2. c4r4pl: four counters up/down, 8/16 bits, parallel load are configured as a 16-bit counter, default is up. Counter sizes can be independently changed to 8 or 16 bits for each bank; default is 16-bit. Once up, down

Contextual Info: 9c M ! ACT 13.3 Volt Field Programmable Gate Arrays Æ F e a tu re s • 3.3 V functionality fully compliant with JEDEC specifications • Up to 2000 Gate Array Gates 6000 PLD equivalent gates • Replaces up to 50 TTL Packages • Replaces up to twenty 20-Pin PAL Packages

Contextual Info: STM32F427xx ARM Cortex-M4 32b MCU+FPU, 210DMIPS, up to 2MB Flash/256+4KB RAM, USB OTG HS/FS, Ethernet, 17 TIMs, 3 ADCs, 20 comm. interfaces & camera Datasheet − production data • Up to 17 timers: up to twelve 16-bit and two 32bit timers up to 168 MHz, each with up to 4

Contextual Info: STM32F437xx ARM Cortex-M4 32b MCU+FPU, 210DMIPS, up to 2MB Flash/256+4KB RAM, crypto, USB OTG HS/FS, Ethernet, 17 TIMs, 3 ADCs, 20 comm. interfaces & camera Datasheet − production data • Up to 17 timers: up to twelve 16-bit and two 32bit timers up to 168 MHz, each with up to 4

A1020A

Abstract: PH 84 CNT4A T-46 FADD32 ACTEL A1010A DLM8
Contextual Info: ACTEL CORP Æ te M 53E D • QnSMRf ci DDDD373 D23 *A C T ACT 1 Field Programmable Gate Arrays I Features Description • Up to 2000 Gate Array Gates 6000 PLD/LCA™ equivalent gates • Replaces up to 53 TTL Packages • Replaces up to 17 20-Pin PAL™ Packages

Contextual Info: ACT 1 and A C T 2 Military Field P rogram m able G ate Arrays ACT 1 Features ACT 2 Features • Up to 2000 Gate Array Gates 6000 PLD/LCA™ equivalent gates • Replaces up to 53 TTL Packages • Replaces up to 17 20-Pin PAL Packages • Design Library with over 250 Macros

A1415

Abstract: A1425 A1425A-3 A1440 A1460 Ai46 ami 0.6 micron ami equivalent gates AI460A
Contextual Info: Axelerator Series FPGAs - yO 3 Family Features Replaces up to twenty 32 macro-cell CPLDs • Up to 10,000 Gate Array Equivalent Gates up to 25,000 equivalent PLD Gates Replaces up to one hundred 20-pin PAL Packages • Highly Predictable Performance with 100%Automatic

A1020A-CQ84B

Abstract: actel package mechanical drawing 5962-9096501MXX TA273 actel a1240 A1020APG84B smd transistor l7 A1020A-JQ84B DEC4X16A "alu 4 bit"
Contextual Info: ACT 1 and ACT 2 Military Field Programmable Gate Arrays ACT 1 Features ACT 2 Features • Up to 2000 Gate Array Gates 6000 P L D / L C A ™ equivalent gates • Up to 8000 Gate A rray Gates (20,000 P L D /L C A ™ equivalent gates) • Replaces up to 53 T T L Packages

Contextual Info: RKP-1U Rack System 2000~6000W Front End Power System ¡½ Features : ¡E¡E E¡ ¡E¡E ¡E¡E ¡E¡E ¡E¡E Universal AC input / Full range Holds up to 3 power modules Active current sharing up to 6000W 3 unit in one 19”rack, 3 rack max. can be operated in parallel (up to 9 units)

Contextual Info: Accelerator Series FPGAs - A C T 3 Family Features Replaces up to twenty 32 macro-cell CPLDs • Replaces up to one hundred 20-pin PAL Packages Up to 10,000 Gate Array Equivalent Gates u p to 25,000equivalent PLD Gates • Up to 1153 Dedicated Flip-Flops

Contextual Info: BACK Accelerator Series FPGAs – ACT 3 PCI-Compliant Family Features • Up to 10,000 Gate Array Equivalent Gates. • Up to 250 MHz On-Chip Performance. • 9.0 ns Clock-to-Output. • Up to 1,153 Dedicated Flip-Flops. • Up to 228 User-Programmable I/O Pins.

ACT 3 Accelerator

Abstract: ACT 3 accelerator FPGAs Actel Accelerator fpga datasheet DLM8 A1425A-3
Contextual Info: Accelerator Series FPGAs – ACT 3 PCI-Compliant Family Features • Up to 10,000 Gate Array Equivalent Gates. • Up to 250 MHz On-Chip Performance. • 9.0 ns Clock-to-Output. • Up to 1,153 Dedicated Flip-Flops. • Up to 228 User-Programmable I/O Pins.

A1415

Abstract: A1425 A1425A-3 A1440 A1460 Actel Accelerator fpga A1460 actel
Contextual Info: Accelerator Series FPGAs – ACT 3 Family Features • Replaces up to twenty 32 macro-cell CPLDs • Up to 10,000 Gate Array Equivalent Gates up to 25,000 equivalent PLD Gates • Replaces up to one hundred 20-pin PAL Packages • Highly Predictable Performance with 100% Automatic

MM1027N

Abstract: ccont mitsumi variable capacitor MM1027NF MM1027NV MM1027XD MM1027XF MM1027XV MM1081XV
Contextual Info: System Reset with battery back-up MM1027, 1081 MITSUMI System Reset (with battery back-up) Monolithic IC MM1027, 1081 Outline These ICs were developed for STATIC-RAM (S-RAM) battery back-up, and have built-in switching circuit for main power supply and battery, back-up timing circuit and battery checker.

MM1081XV

Contextual Info: System Reset with battery back-up MM1027, 1081 MITSUMI System Reset (with battery back-up) Monolithic IC MM1027, 1081 Outline These ICs were developed for STATIC-RAM (S-RAM) battery back-up, and have built-in switching circuit for main power supply and battery, back-up timing circuit and battery checker.

SiS 486 schematic

Contextual Info: Accelerator Series FPGAs - ACT 3 Family Features • Replaces up to twenty 32 macro-cell CPLDs • Up to 10,000 Gate Array Equivalent Gates up to 25,000 equivalent P L IJ Gates • Replaces up to one hundred 20-pin PAL Packages • Highly Predictable Performance with 100% Automatic