UG362 Search Results

phase shift oscillator

Abstract: vhdl code for phase shift XC6VLX240T DSP48E1 UG362 XC6VLX760 VIRTEX-6 UG362
Contextual Info: Virtex-6 FPGA Clocking Resources User Guide [optional] UG362 v1.0 June 24, 2009 [optional] Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit the

UG362

Abstract: VIRTEX-6 UG362 vhdl code for phase shift customer reference board 2011 UG365 DSP48E1 XC6VLX760 UG-362
Contextual Info: Virtex-6 FPGA Clocking Resources User Guide UG362 v1.6 January 17, 2011 Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit the

DSP48E1

Abstract: UG362 XC6VLX760 VIRTEX-6 UG362
Contextual Info: Virtex-6 FPGA Clocking Resources User Guide UG362 v1.4 April 7, 2010 Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit the

UG365

Abstract: UG-361 XC6VLX240T UG365 XC6VLX240T-1FFG1156 DSP48E1 VIRTEX-6 UG362 write operation using ram in fpga xc6vlx240t VIRTEX-6 UG373 frequency detection using FPGA
Contextual Info: → 11 Virtex-6 Family Overview DS150 v2.4 January 19, 2012 Product Specification General Description The Virtex -6 family provides the newest, most advanced features in the FPGA market. Virtex-6 FPGAs are the programmable silicon foundation for Targeted Design Platforms that deliver integrated software and hardware components to enable designers to focus on

DSP48E1

Abstract: FPGA Virtex 6 LXT virtex 6 XC6VSX475T XC6VLX240T-1FFG1156 "Binary Multipliers" UG-361 virtex+6 UG366 1000BASE-X DS150
Contextual Info: 11 Virtex-6 Family Overview DS150 v2.1 November 6, 2009 Advance Product Specification General Description The Virtex -6 family provides the newest, most advanced features in the FPGA market. Virtex-6 FPGAs are the programmable silicon foundation for Targeted Design Platforms that deliver integrated software and hardware components to enable designers to focus on

XC6VLX240T-1FFG1156

Abstract: XC6VLX240T-1FFG DSP48E1 TEMAC XC6VLX240T-1FFG1156C XC6VLX240T UG366 XC6VLX130T UG-361 Virtex 6
Contextual Info: → 11 Virtex-6 Family Overview DS150 v2.2 January 28, 2010 Advance Product Specification General Description The Virtex -6 family provides the newest, most advanced features in the FPGA market. Virtex-6 FPGAs are the programmable silicon foundation for Targeted Design Platforms that deliver integrated software and hardware components to enable designers to focus on

DS-INMP441

Contextual Info: INMP441 Omnidirectional Microphone with Bottom Port and I2S Digital Output APPLICATIONS GENERAL DESCRIPTION The INMP441 is a high-performance, low power, digital-output, omnidirectional MEMS microphone with a bottom port. The complete INMP441 solution consists of a MEMS sensor, signal

Contextual Info: 49 Virtex-6 CXT Family Data Sheet DS153 v1.0 July 8, 2009 Advance Product Specification General Description Virtex -6 CXT FPGAs provide designers needing power-optimized 3.75 Gb/s transceiver performance with an optimized ratio of built-in system-level blocks. These include 36 Kb block RAM/FIFOs, up to 15 Mb of block RAM, up to 768 DSP48E1

XC6VLX240T-1FFG1156

Abstract: XC6VLX760 XC6VLX240T-1FFG DSP48E1 Virtex Analog to Digital Converter XC6VLX240T-1FFG1156C DS150 SRL16 XC6VLX130T XC6VLX195T
Contextual Info: → 11 Virtex-6 Family Overview DS150 v2.3 March 24, 2011 Preliminary Product Specification General Description The Virtex -6 family provides the newest, most advanced features in the FPGA market. Virtex-6 FPGAs are the programmable silicon foundation for Targeted Design Platforms that deliver integrated software and hardware components to enable designers to focus on

netlogic tcam

Abstract: TCAM netlogic
Contextual Info: ML631 Virtex-6 HXT FPGA Packet Processor/Traffic Manager Evaluation Board User Guide UG841 v1.0 March 9, 2012 Notice of Disclaimer The information disclosed to you hereunder (the “Materials”) is provided solely for the selection and use of Xilinx products. To the maximum

mems microphone

Contextual Info: Omnidirectional Microphone with Bottom Port and I2S Digital Output ADMP441 Data Sheet FEATURES FUNCTIONAL BLOCK DIAGRAM Digital I²S interface with high precision 24-bit data High SNR of 61 dBA High sensitivity of −26 dBFS Flat frequency response from 60 Hz to 15 kHz

XAPP878

Abstract: UG362 VIRTEX-6 VIRTEX-6 UG362 verilog code for shift register UG-362 lookup table
Contextual Info: Application Note: Virtex-6 Family MMCM Dynamic Reconfiguration Author: Karl Kurbjun and Carl Ribbing XAPP878 v1.1 June 9, 2010 Summary This application note provides a method to dynamically change the clock output frequency, phase shift, and duty cycle of the Virtex -6 FPGA mixed-mode clock manager (MMCM)

XAPP878

Abstract: UG362 VIRTEX-6 UG362 verilog code for 8 bit shift register
Contextual Info: Application Note: Virtex-6 Family MMCM Dynamic Reconfiguration Author: Karl Kurbjun and Carl Ribbing XAPP878 v1.0 March 22, 2010 Summary This application note provides a method to dynamically change the clock output frequency, phase shift, and duty cycle of the Virtex -6 FPGA mixed-mode clock manager (MMCM)

FFG1156

Abstract: HSLVDCI15 XC6VCX130 MGTRXP0 VIRTEX-6 UG362 UG-361 UG365 UG366 DSP48E1 SRL16
Contextual Info: 48 Virtex-6 CXT Family Data Sheet DS153 v1.1 February 5, 2010 Advance Product Specification General Description Virtex -6 CXT FPGAs provide designers needing power-optimized 3.75 Gb/s transceiver performance with an optimized ratio of built-in system-level blocks. These include 36 Kb block RAM/FIFOs, up to 15 Mb of block RAM, up to 768 DSP48E1

UG-361

Abstract: 1000BASE-X DSP48E1 SRL16 VIRTEX-6 UG362 ds152 VIRTEX-6 UG360 lvdci18 Virtex 6 CXT FF484
Contextual Info: 52 Virtex-6 CXT Family Data Sheet DS153 v1.6 February 11, 2011 Product Specification General Description Virtex -6 CXT FPGAs provide designers needing power-optimized 3.75 Gb/s transceiver performance with an optimized ratio of built-in system-level blocks. These include 36 Kb block RAM/FIFOs, up to 15 Mb of block RAM, up to 768 DSP48E1

Contextual Info: ML623 Virtex-6 FPGA GTX Transceiver Characterization Board User Guide UG724 v1.1 September 15, 2010 Xilinx is disclosing this user guide, manual, release note, and/or specification (the “Documentation”) to you solely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit the

Contextual Info: Omnidirectional Microphone with Bottom Port and I2S Digital Output ADMP441 Data Sheet FEATURES FUNCTIONAL BLOCK DIAGRAM I2S SERIAL PORT HARDWARE CONTROL SCK SD WS 09568-001 L/R CHIPEN GND GND VDD POWER MANAGEMENT FILTER TE Figure 1. BOTTOM TOP 09568-015 Teleconferencing systems

example ml605 FMC 150

Abstract: XAPP1071 VHDL code for ADC and DAC SPI with FPGA OSERDES VHDL code for ADC and DAC SPI with FPGA spartan 3 example ml605 FMC-101 Verilog code for ADC and DAC SPI with FPGA XC6VLX240T-2-FF1156 ISERDES
Contextual Info: Application Note: Virtex-6 FPGAs Connecting Virtex-6 FPGAs to ADCs with Serial LVDS Interfaces and DACs with Parallel LVDS Interfaces XAPP1071 v1.0 June 23, 2010 Author: Marc Defossez Summary This application note describes how to utilize the dedicated deserializer (ISERDES) and

Contextual Info: ADMP441 Omnidirectional Microphone with Bottom Port and I2S Digital Output APPLICATIONS GENERAL DESCRIPTION The ADMP441 is a high-performance, low power, digital-output, omnidirectional MEMS microphone with a bottom port. The complete ADMP441 solution consists of a MEMS sensor, signal

Application note I2s

Abstract: sck 104 capacitor
Contextual Info: Omnidirectional Microphone with Bottom Port and I2S Digital Output ADMP441 Data Sheet FEATURES FUNCTIONAL BLOCK DIAGRAM Digital I²S interface with high precision 24-bit data High SNR of 61 dBA High sensitivity of −26 dBFS Flat frequency response from 60 Hz to 15 kHz

DSP48E1

Abstract: XC6VLX240T-1FFG1156C Virtex 6 VIRTEX-6 UG365 XC6VLX240T-1FFG1156 XC6VLX130T VIRTEX-6 UG362 XC6VLX240T FF1759 VIRTEX-6 UG360
Contextual Info: 9 Virtex-6 Family Overview DS150 v1.2 June 24, 2009 Advance Product Specification General Description The Virtex -6 family provides the newest, most advanced features in the FPGA market. Using the third generation ASMBL (Advanced Silicon Modular Block) column-based architecture, the Virtex-6 family contains multiple distinct sub-families. This overview covers the

Contextual Info: ML628 Virtex-6 FPGA GTX and GTH Transceiver Characterization Board User Guide UG771 v1.1 February 19, 2014 Notice of Disclaimer The information disclosed to you hereunder (the “Materials”) is provided solely for the selection and use of Xilinx products. To the maximum

Contextual Info: ML630 Virtex-6 HXT FPGA Optical Transmission Network Evaluation Board User Guide UG828 v1.0 September 28, 2011 The information disclosed to you hereunder (the "Materials") is provided solely for the selection and use of Xilinx products. To the maximum extent permitted by applicable law: (1) Materials are made available "AS IS" and with all faults, Xilinx hereby DISCLAIMS ALL

XC6VLX240T-1FFG1156

Abstract: virtex-6 ML605 user guide example ml605 FMC 150 example ml605 ML605 ML605 DVI ml605 bom xilinx DDR3 controller user interface UG533 ddr3 ram repair
Contextual Info: Getting Started with the Xilinx Virtex-6 FPGA ML605 Evaluation Kit [Guide Subtitle] [optional] UG533 v1.4 November 15, 2010 [optional] XPN 0402771-01 Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development