TXD30 Search Results

Contextual Info: DATA SHEET MOS INTEGRATED CIRCUIT µPD98431 10/100 Mbps Ethernet TM CONTROLLER DESCRIPTION The µPD98431 is a 10/100 Mbps Ethernet controller having eight Media Access Control MAC ports conforming to IEEE 802.3 and IEEE 802.3u. Each port can store 1 packet of receive data since each port has a 2 KB receive FIFO. This can reduce the

Contextual Info: TLK3118 Redundant XAUI Transceiver www.ti.com • • • • • • • • • • • Fabricated in Advanced 130-nm CMOS Technology Package: Small Footprint 21x21mm, 400-Ball, Fine Pitch 1mm PBGA TLK3118 TDP/N[3:0]0 TCLK TD(31.0) TC(3.0) RCLK RD(31.0)

Contextual Info: Preliminary Data Sheet August 1998 microelectronics group Lucent Technologies Bell Labs Innovations TTSI2K32T 2048-Channel, 32-Highway Time-Slot Interchanger Features Applications • Thirty-two full-duplex, serial time-division multi­ plexed TDM highways.

100base

Abstract: NWK933 Mitel Semiconductor process flow
Contextual Info: NWK933 NWK933 3.3V 10/100 Fast Ethernet Transceiver to MII DS5029 Issue no 2.1 May 1999 Features Odering Information ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● Integrated 10/100 Mbps Ethernet in a Single Chip Solution Single 3.3V Power Supply

SMD codes

Abstract: 063310
Contextual Info: QuadPHY 10GX ASSP Telecom Standard Product Data Sheet Released PM8358 QuadPHY® 10GX 4 X 1.2 to 3.2 Gbit/s Quad, Fully Redundant, XAUI to XGMII, 10 Gigabit Ethernet / Fibre Channel Physical Layer Device Data Sheet Released Issue No. 5: April 2004 Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.

sony rxd7

Abstract: w1p13 XMT 2315 8B10B RXD14 3156 00010001
Contextual Info: 8101 8101 Gigabit Ethernet Controller 99110 This document is an LSI Logic document. Any reference to SEEQ Technology should be considered LSI Logic. Note: Check for latest Data Sheet revision before starting any designs. SEEQ Data Sheets are now on the Web, access

bv228

Abstract: S1C33210 S1C33L01 MF1517-01 CP4D
Contextual Info: MF1517-01 CMOS 32-BIT SINGLE CHIP MICROCOMPUTER S1C33210 Technical Manual S1C33210 PRODUCT PART S1C33210 FUNCTION PART NOTICE No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice.

Contextual Info: LAN83C180 PRELIMINARY 10/100 Fast Ethernet PHY Transceiver FEATURES § § § § § § § § § § § § Single Chip 100Base-TX/10Base-T Ethernet Physical Layer PHY Solution Dual Speed – 10/100 Mbps Full MII Interface for a Glueless MAC Connection MI Interface for Configuration and Status

chilled water system

Contextual Info: Data Sheet, Revision 3 September 21, 2005 TSI-2 2k x 2k Time-Slot Interchanger 1 Introduction The last issue of this data sheet was August 31, 2005. A change history is included in Section 11 Change History on page 61. Red change bars have been installed on all text, figures, and tables that were added or changed. All changes to the text

GMII

Abstract: TC9208M TC9208M-DS-R06 txer6
Contextual Info: TC9208M Preliminary Data Sheet 8-Port 10/100/1000 Smart Ethernet Switch This feature allows improved multimedia applications. Features Stand Alone Switch On A Chip 8 Ethernet 10/100/1000 ports MII/GMII interface for all ports Trunk group support Four Classes of Service CoS selectable for

GSM jamming scheme generator

Abstract: "IEEE 802.3" "Clause 27" BRXD12 BTXD02 APAA LUC3R04 S5241 OXCO LUC3S02 BTXD10
Contextual Info: Preliminary Data Sheet July 1997 microelectronics group Lucent Technologies Bell Labs Innovations LUC3R04 10/100 Mbits/s Managed Repeater CMOS Integrated Circuit Features • Four single repeaters per chip allow for port mobil­ ity repeater designs similar to those based on the

y12 t 953

Abstract: TC9205M 100/1000 gigabit Integrated Switch with PHY GMII VLAN Tag TC9205M-DS-R03 Ethernet Switch Controller TC9205 Tc9025
Contextual Info: TC9205M Preliminary Data Sheet 5-Port 10/100/1000 Smart Ethernet Switch This feature allows improved multimedia applications. Features Stand Alone Switch On A Chip 5 Ethernet 10/100/1000 ports I Ethernet 10/100 port MII/GMII interface for 5 ports I extra MII interface for 6th port

1000BASE-X

Abstract: DP83821 PC99 TCI D2S f f8fch 93c06 national semiconductor AL-2001
Contextual Info: February 2001 DP83821 10/100/1000 Mb/s PCI Ethernet Network Interface Controller General Description DP83821 is a single-chip 10/100/1000 Mb/s Ethernet Controller for the PCI bus. It is targeted at highperformance adapter cards and mother boards. The DP83821 fully implements the V2.2 33 MHz, 32-bit PCI bus

NETARM

Contextual Info: NET+Works for NET+ARM Hardware Reference Guide TM This guide provides a description of the NET+ARM 15/40 hardware. Part Number/Version: 8833198D Release Date: September, 2000 NETsilicon, Inc. 411 Waverley Oaks Road Suite 227 Waltham, MA 02452 Tel: 781 647-1234 or (800) 243-2333

net eN8

Abstract: TDN01 crpa 8B10B P802 TLK3118 XGXS quad video processor
Contextual Info: TLK3118 Redundant XAUI Transceiver www.ti.com SLLS628C – DECEMBER 2004 – REVISED APRIL 2007 • • • • • • • • • • • Technology Package: Small Footprint 21x21mm, 400-Ball, Fine Pitch 1mm PBGA TLK3118 TDP/N[3:0]0 TCLK TD(31.0) TC(3.0)

RXD55

Abstract: RXD26
Contextual Info: Hardware Design Guide June 2004 STSI-144 Scalable Time-Slot Interchanger Hardware Design Guide Introduction Related Documents This document describes the hardware interfaces to Agere Systems Inc. scalable time-slot interchanger STSI-144 device. Information relevant to the use of

highway speed checker

Abstract: highway speed checker application only SPEED CHECKER FOR HIGHWAY highway speed checker circuit diagram highway speed checker block diagram
Contextual Info: Data Sheet December 2004 TTSI4K32T 4096-Channel, 32-Highway Time-Slot Interchanger Features „ „ „ „ „ „ „ „ „ „ „ „ „ „ „ „ „ „ „ „ „ Thirty-two full-duplex, serial time-division multiplexed TDM highways. Full availability, nonblocking 4096-channel time/

Contextual Info: CMOS 32-BIT SINGLE CHIP MICROCOMPUTER S1C33301 Technical Manual NOTICE No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any

TS127 08

Abstract: RXD55 RXD01 txd45 RXD4-8 RXD35 TSI-16 RXD26 TXD38 TXD37
Contextual Info: Advance Information May 2003 TSI-16 Time-Slot Interchanger Hardware Design Guide Introduction Related Documents This document describes the hardware interfaces to Agere Systems Inc. TSI-16 device. Information relevant to the use of the device in a board design is covered. Ball descriptions, dc electrical characteristics,

K297

Abstract: net eN8 TDN01
Contextual Info: TLK3118 Redundant XAUI Transceiver www.ti.com SLLS628C – DECEMBER 2004 – REVISED APRIL 2007 • • • • • • • • • • • Technology Package: Small Footprint 21x21mm, 400-Ball, Fine Pitch 1mm PBGA TLK3118 TDP/N[3:0]0 TCLK TD(31.0) TC(3.0)

ap1448

Abstract: 45x45 bga an6169 RXFD65 Rxd07 734 B34 8B10B PD98431 C3258 709 B34
Contextual Info: PRELIMINARY DATA SHEET MOS INTEGRATED CIRCUIT µPD98433 TM 10/100/1000 Mbps Ethernet Controller The µPD98433 is a 10/100/1000 Mbps Ethernet controller with eight-port internal Media Access Control MAC function that complies with the IEEE Standard 802.3 1998 Edition.

transistor NEC D 882 p

Abstract: nec d 882 p datasheet SKR 50 a1275 MOS 6581 transistor NEC D 587 SI 356/2 diode nec d 882 p pwm Generator 2-423 NEC V30
Contextual Info: Design Manual CB-9 Family VX/VM Type Core Library 0.35 µm CMOS Cell-Based IC CBIC CPU Core, Memory Controller 78K/0 Core V851TM Core V853TM Core V30MXTM V30MZTM NB85E NB85E901 NB85ET NB85E500 NU85E500 NU85E502 Document No. A13195EJ5V1DM00 (5th edition)

8B10B

Abstract: P802 TLK3118 RXD17
Contextual Info: TLK3118 Redundant XAUI Transceiver www.ti.com • • • • • • • • • • • Fabricated in Advanced 130-nm CMOS Technology Package: Small Footprint 21x21mm, 400-Ball, Fine Pitch 1mm PBGA TLK3118 TDP/N[3:0]0 TCLK TD(31.0) TC(3.0) RCLK RD(31.0)

SA4-13

Abstract: AUB-13 EFL 231 m25c22
Contextual Info: Lucent Technologies Bell Labs Innovations TFRA08C13 Octal T1/E1 Framer Preliminary Data Sheet November 1998 microelectronics group Lucent Technologies Bell Labs Innovations TFRA08C13 Octal T1/E1 Framer Features Facility Data Link Features • Eight independent T1/E1 transmit and receive