TXCL Search Results

1 phase pure sine wave inverter schematic

Abstract: INT5130 inverter PURE SINE WAVE schematic diagram powerline schematic diagram D1 PGA 478 design pure "sine wave" power inverter OFDM FFT powerline carrier transmission schematic powerline V.96 Modem
Contextual Info: Broadband Modem Mixed-Signal Front End AD9865 FUNCTIONAL BLOCK DIAGRAM AD9865 PWR DWN MODE TXEN/SYNC TXCLK 2-4X IAMP TxDAC 0 TO –7.5dB IOUT_G+ IOUT_N+ IOUT_N– IOUT_G– 0 TO –12dB 10 CLKOUT_1 CLKOUT_2 CLK SYN. ADIO[9:4]/ Tx[5:0] 2M CLK MULTIPLIER OSCIN

Contextual Info: Broadband Modem Mixed-Signal Front End AD9869 Broadband wireline networking AD9869 2-4X PWRDWN MODE TXEN/TXSYNC TXCLK/TXQUIET IAMP TxDAC 12 0 TO –7.5dB IOUTN– 0 TO –12dB CLKOUT1 CLKOUT2 CLK SYNC. ADIO[11:6]/ Tx[5:0] IOUTN+ 2M CLK MULTIPLIER OSCIN XTAL

LC51024MB-52F484C

Abstract: LFX500B-05F516C
Contextual Info: UTOPIA Level 3 ATM Transmit Interface December 2003 IP Data Sheet Features General Description • Fully Compatible with ATM Forum UTOPIA Level 3 Specifications ■ Supports Single-PHY and Multi-PHY Operation Modes ■ Multi-PHY Operation with Single txclav

Contextual Info: Broadband Modem Mixed-Signal Front End AD9866 FUNCTIONAL BLOCK DIAGRAM AD9866 PWR DWN MODE TXEN/SYNC TXCLK 2-4X IAMP TxDAC 0 TO –7.5dB IOUT_G+ IOUT_N+ IOUT_N– IOUT_G– 0 TO –12dB 12 CLKOUT_1 CLKOUT_2 CLK SYN. ADIO[11:6]/ Tx[5:0] 2M CLK MULTIPLIER OSCIN

7474

Abstract: QS6611 SW-SPsT datasheet 7474 MX98741 QS162244FCT TSC25 sw-SPST-2 of 7474 of d sw spst
Contextual Info: A B C +5V D E G H I J HUB A QS162244FCT 9 F 9 QS6611 R1 10K TXD[0.4] X1 28 20 TSC25 U?A 7474 4 2 50 Mhz 3 PR 8 D Q QS6611 5 CL Q X1 8 TXD[0.4] CLK MX98741 X1 28 6 TSC25 20 1 QS6611 TXCLK TXD[0.4] X1 28 7 7 TXCLK 20 Closed to use as Master clock / Open to use as Slave

50MHz VCO

Abstract: D1 PGA 478 OFDM FPGA AD9865 AD9866 AD9876 AD9975 PBR951
Contextual Info: Broadband Modem Mixed Signal Front End AD9866 Powerline networking VDSL and HPNA AD9866 PWR DWN MODE TXEN/SYNC TXCLK 2-4X IAMP TxDAC 0 TO –7.5dB IOUT_G+ IOUT_N+ IOUT_N– IOUT_G– 0 TO –12dB 12 CLKOUT_1 CLKOUT_2 CLK SYN. ADIO[11:6]/ Tx[5:0] 2M OSCIN XTAL

hfdw

Contextual Info: _ ü 16/18Mbit 2Mx8/9 & 64/72Mbit (8Mx8/9) ConcurrentRDRAM Overview VDD GND BUSDATA[8] GND BUSDATA[7] (NC) BUSENABLE VDD BUSDATA[6] GND BUSDATA[5] VDDA RXCLK GNDA TXCLK VDD BUSDATA[4] GND BUSCTRL SIN VREF SOUT BUSDATA[3] GND BUSDATA[2] (NC)

RTL8201BL schematic

Abstract: RTL8130 VDD33C RJ8-45 rxer rxd1 MDIO RTL8139C schematic rtl81 RTL8201BL
Contextual Info: A B R33 1.5K VDD33 4 25 26 6 5 4 3 2 7 22 21 20 19 18 16 1 23 24 46 47 Y1 C5 25.000Mhz 20P GND LED0/PHYAD0 LED1/PHYAD1 LED2/PHYAD2 LED3/PHYAD3 LED4/PHYAD4 C6 20P GND PWFBIN VDD33 VDD33 PWFBIN D E U1 MDC MDIO TXD0 TXD1 TXD2 TXD3 TXEN TXCLK RXDV RXD0 RXD1 RXD2

Contextual Info: Broadband Modem Mixed-Signal Front End AD9866 IOUT_P+ AD9866 PWR DWN MODE TXEN/SYNC TXCLK 2-4X 0 TO –7.5dB IOUT_G+ IOUT_N+ IOUT_N– IOUT_G– 0 TO –12dB 12 CLKOUT_1 CLKOUT_2 CLK SYN. ADIO[11:6]/ Tx[5:0] 2M CLK MULTIPLIER OSCIN XTAL ADIO[5:0]/ Rx[5:0]

Contextual Info: Broadband Modem Mixed-Signal Front End AD9868 FEATURES Broadband wireline networking IOUTP– AD9868 2-4X PWRDWN MODE TXEN/TXSYNC TXCLK/TXQUIET IAMP TxDAC 10 0 TO –7.5dB IOUTN– 0 TO –12dB CLKOUT1 CLKOUT2 CLK SYNC. ADIO[9:4]/ Tx[5:0] IOUTN+ 2M CLK MULTIPLIER

16bit microprocessor using vhdl

Abstract: vhdl code 16 bit microprocessor design of micro architecture using VHDL vhdl code for asynchronous fifo 8 bit microprocessor using vhdl atm source code vhdl code for 555 parallel interface vhdl
Contextual Info: Product Brief August 2000 ATM UTOPIA Slave Core V2.0 UTOPIA Level 1/Level 2 with parity generation/ checking. In Level 2, all multi-PHY modes are supported: — 1 RxClav/1 TxClav — Direct status — Multiplexed status polling • 8-/16-bit bus width ■

16bit microprocessor using vhdl

Abstract: vhdl code for phy interface vhdl code 16 bit microprocessor 4 bit microprocessor using vhdl 8 bit microprocessor using vhdl ATM-UTOPIA-Master-Core 16 bit data bus using vhdl parallel interface vhdl vhdl code 8 bit microprocessor 4 bit Microprocessor VHDl code
Contextual Info: odel are Product Brief ATM UTOPIA Master Core V2.0  Standards to Silicon March 1999 Features • UTOPIA Level 1/Level 2 Master with parity generation/checking. In Level 2, all "multi PHY" modes are supported: ⇒ 1 RxClav/1 TxClav ⇒ Direct Status ⇒ Multiplexed Status Polling

avnet

Abstract: error correction code in vhdl CH-2555 vhdl code for fifo vhdl code switch layer 2 Branding D53 APA150 OC48 vhdl code for asynchronous fifo
Contextual Info: AvnetCore: Datasheet Version 1.0, July 2006 UTOPIA Level 3 Link Intended Use: — Cell Processors — Switch Fabrics — Networking — Telecommunications top_master.vhd Features: top_egr_master.vhd — Function compatible with ATM Forum wr_enb rd_enb txclk

48 MHz Crystal

Abstract: WE MIDCOM 74 Am27C512-D R2716 SIP 9 JP1 P31A IDT71256 TP10 XA11 XA14
Contextual Info: A B C D E XD[0:7] POWER-ON RESET VCC XA[0:15] 32Kx8 SRAM VCC U1 D1 TP1 R1 4 TP4 TP5 TP6 TP7 TP8 C1 1uF + TP9 TP10 TP11 TP12 TP13 TP14 NC NC NC NC NC NC NC NC NC TP3 TP15 67 TP19 68 LINK_LED 57 TxD TxEN TxCLK RxD RxCLK PHYCRS PHYCOL 62 14 16 29 32 30 31 15

74HC04

Abstract: 74HC00 74HC04 NOT GATE datasheet SW-DIP-8 rp1 10k SW-SPDT sw dip-8 16DIP300 SW-DIP-8 datasheet XRT75VL00
Contextual Info: 5 4 3 2 1 RP1 10K 10HEADER VDD3 R1 R9 R8 R7 R6 R5 R4 R3 R2 COM 1 VDD VDD PARALLEL PORT D04 D4 DB25 P5 D04 D3 D04 D2 RXMON IN4148 1 14 2 15 3 16 4 17 5 18 6 19 7 20 8 21 9 22 10 23 11 24 12 25 13 R5 HOST/HW* SR/DR* LOSMUTEN RXON RXCLKINV TXCLKINV RXMON 500

AD9865

Abstract: AD9868 AD9869
Contextual Info: Broadband Modem Mixed-Signal Front End AD9868 Broadband wireline networking AD9868 2-4X PWRDWN MODE TXEN/TXSYNC TXCLK/TXQUIET IAMP TxDAC 10 0 TO –7.5dB IOUTN– 0 TO –12dB CLKOUT1 CLKOUT2 CLK SYNC. ADIO[9:4]/ Tx[5:0] IOUTN+ 2M CLK MULTIPLIER OSCIN XTAL

BAT54 COL

Abstract: UIO12 TINIs400 NC128 NC132 UIO30 nc86 dio sc bat54 DS2408 NC81
Contextual Info: nPCE2 P52 P51 P50 A18 nC E2 nC E1 nC E0 P67 P66 A21 nC E7 nC E6 nC E5 nC E4 nC E3 P 1[7:0] nPCE3 P33 nPCE0 P 3[3:0] P31 P53 P32 nPCE1 P 5[3:0] P30 P 6[7:6] R xD0 R xD1 R xD2 R xD3 n R stIn TxClk R x C lk n R s t O ut TxD3 TxD2 TxD1 TxD0 TxEn CRS TxEn C OL

I2S fifo

Abstract: demultiplexing
Contextual Info: FJS 01/28/97 Block diagram and functional description of UTOPIA master to connect two or more PHY chips back-to-back RxCLAV RxENB TxCLAV IWE2SDHT Controller RxSOC IWE8 ATMCLK TxENB TxSOC 19.44 MHz up to 26 MHz Clock Source TxCLAV ATMCLK SDHT RxCLAV SDHT2IWE

RTL8201CL

Abstract: RTL8201BL schematic RTL8201BL RJ8-45 RTL8201CP schematic H1251 RTL8201CP 8201BL h1245 AVDD33
Contextual Info: A B R31 1.5K VDD33 4 MDC MDIO TXD0 TXD1 TXD2 TXD3 TXEN TXCLK RXDV RXD0 RXD1 RXD2 RXD3 RXCLK COL CRS RXER Connect to MAC which has MII interface 25 26 6 5 4 3 2 7 22 21 20 19 18 16 1 23 24 46 47 Y1 C5 25.000Mhz 20P GND LED0/PHYAD0 LED1/PHYAD1 LED2/PHYAD2 LED3/PHYAD3

RJ8-45

Abstract: RTL8201BL RTL8201BL schematic AVDD33 PE68515 LM1117 LQFP48 VDD33 pe-68515 2r250
Contextual Info: A B C D E U1 25 26 6 5 4 3 2 7 22 21 20 19 18 16 1 23 24 46 47 TXD0 4 Connect to MAC which has SNI interface TXEN TXCLK RXD0 RXCLK COL CRS Y1 C5 25.000Mhz 20P GND LED0/PHYAD0 LED1/PHYAD1 LED2/PHYAD2 LED3/PHYAD3 LED4/PHYAD4 C6 20P 9 10 12 13 15 PWFBIN 8 VDD33

Contextual Info: UPD71051G 1/3 IL08D C-MOS SERIAL CONTROLLER —TOP VIEW— 44 43 42 41 40 39 38 37 36 35 34 NC NC NC 1 15 16 NC 33 18 NC 32 19 NC 2 NC 3 31 4 30 5 29 25 26 27 29 D0 D1 DSR D2 RXCLK D3 RXDATA D4 TXCLK D5 CTS 27 8 26 9 25 NC 24 10 NC 4 TXRDY CK TXEMP 36 37

SpaceWire

Abstract: 0X0112 spw -136 0588 0X0111 ECSS-E-ST-50-12C
Contextual Info: Aeroflex Colorado Springs ERRATA ERR-SPW-003-01 Invalid TXCLK_IN and Initialization Divide Register Combination for UT200SpW4RTR SpaceWire Router Product Name: Table 1: Cross Reference of Applicable Products Manufacturer Part SMD # Number 4-PORT SPACEWIRE ROUTER

Contextual Info: VDDA T 3.3V ~ 9 r T 1.8V or 3.3V VDD 1r ~9r T ~9r T -9 r VDDPLL VDD VDDPLL VDD IOVDD VDD T TxCLKIN TxlN31 TxlN30 TxlN29 TxlN28 TxlN27 TxlN26 TxlN25 TxlN24 TxlN23 TxlN22 TxlN21 TxlN20 TxlN19 TxlN18 TxlN17 < 3.3V 1r TxlN16 TxlN15 TxlN14 TxlN13 TxlN12 TxlN11

74hc04

Abstract: tms 374 74HC04 NOT GATE datasheet ddr5 74HC04 datasheet DMO10 TX3036 dmo2 DMO11 IDC18
Contextual Info: 5 4 3 2 1 VDD TP21 RLOS0 R59 74HC04 RTIP_0 C22 RRING_0 0.01uF TCLK_0 F22 TXCLK_0 TPOS_0 E23 TXPOS_0 TNEG_0 C25 D22 RLOS_0 RLOL_0 G22 RLOL_0 DMO_0 N3 J36 LCV0 RCLK_0 RXPOS_0 E25 RPOS_0 RXNEG/LCV_0 F23 RGND_0 14 RRING_1 R23 37.4 C11 SFMCLK_0 E24 AE22 RTIP_1