TWO-CHANNEL DMA CONTROLLER Search Results

EC38J

Contextual Info: Blackfin Embedded Processor ADSP-BF536 a FEATURES Two dual-channel memory DMA controllers Memory management unit providing memory protection Up to 400 MHz high-performance Blackfin processor Two 16-bit MACs, two 40-bit ALUs, four 8-bit video ALUs, 40-bit shifter

GA27-3093-04

Abstract: c8051 microcontroller 48-Pin TSOP Type 1, CPL C8051 48-Pin TSOP - Type 1, CPL 8051 opcode hexadecimal with mnemonic sheet IA82510 GA27-3093 80C152JA IA80C152
Contextual Info: Page 1 of 32 IA80C152 Preliminary Data Sheet UNIVERSAL COMMUNICATIONS CONTROLLER FEATURES • Form, Fit, and Function Compatible with the Intel 80C152 • Two-Channel DMA With Multiple Transfer Modes • Packaging options available − 48 Pin Plastic or Ceramic DIP

V96SSC25LP

Contextual Info: ‘ÌOOMEOO 0 0 0 0 3 0 3 ISA V96SSC • * * ▼ / Rev. BO HIGH-INTEGRATION SYSTEM CONTROLLER FOR ¡960 Sx/Jx AND PowerPC 401 Gx PROCESSORS • Direct interface to ¡960Sx/Jx and PPC401Gx processors • High-performance burst DRAM controller • Two-channel fly-by DMA controller

CS6220

Abstract: Myson Century cs CS622 voip ethernet single chip Myson cs6220 soc voip gateway 1Mx16 flash
Contextual Info: CS6220 Preliminary 32-Bit SoC MCU for VoIP 1.0 INTRODUCTION 1.1 CO NF ID EN TI AL The CS6220 processor is a high performance system-on-a-chip SoC that combines a unified RISC/DSP processor with a high-speed 32-channel DMA controller, on-chip SRAM, two Ethernet 10/100 Base-T

4453 smd

Abstract: fr 3709 td 1410 040h-7FFFFFh max 1786 nlal 945 SMJ320C31 SMJ320LC31 SMQ320LC31 QAJ SMD
Contextual Info: SMJ320C31, SMJ320LC31, SMQ320LC31 DIGITAL SIGNAL PROCESSORS S G Ü S 0 2 6 -A P R IL 1998 On-Chip Memory-Mapped Peripherals: - One Serial Port Supporting 8-/16-/24-/32-Bit Transfers - Two 32-Bit Timers - One-Channel Direct Memory Access DMA Coprocessor for Concurrent I/O

addressing modes of dual core processor

Abstract: SPRU674 OMAP5910 SPRU672 SPRU675 SPRU678 SPRU690 element14
Contextual Info: OMAP5910 Dual-Core Processor System DMA Controller Reference Guide Literature Number: SPRU674 October 2003 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries TI reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any

C670x

Abstract: block diagram 3 element control C6000 SPRU189 SPRU190 TMS320C6000 harvard TMS320C67X 8000800F
Contextual Info: TMS320C620x/C670x DSP Program and Data Memory Controller/ Direct Memory Access DMA Controller Reference Guide Literature Number: SPRU577A September 2004 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,

intel 8237A DMA Controller

Abstract: 000D 008B 0X0083
Contextual Info: Application Note 029 Programming DMA on PC/XT/AT Computers T. Hayles and D. Potter Introduction Direct Memory Access DMA is a useful and powerful mechanism for transferring data in data acquisition and control applications. A personal computer equipped with a DMA controller can

MC145488FN

Abstract: MC145488 B300 B500 MC145474
Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA Technical Summary MC145488 Dual Data Link Controller This technical summary gives a brief overview of the MC145488 Dual Data Link Controller. The MC145488 is a two–channel ISDN LAPD controller with an on–chip direct memory access DMA controller. It is intended for ISDN terminal

MC145488

Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA Technical Summary MC145488 Dual Data Link Controller This technical summary gives a brief overview of the MC145488 Dual Data Link Controller. The MC145488 is a two–channel ISDN LAPD controller with an on–chip direct memory access DMA controller. It is intended for ISDN terminal

B300

Abstract: B500 MC145474 MC145488 ML145488-4P
Contextual Info: ML145488 Dual Data Link Controller Legacy Device: Motorola MC145488 This technical summary gives a brief overview of the ML145488 Dual Data Link Controller. The ML145488 is a two–channel ISDN LAPD controller with an on–chip direct memory access DMA controller. It is intended for ISDN

Contextual Info: ML145488 Dual Data Link Controller Legacy Device: Motorola MC145488 This technical summary gives a brief overview of the ML145488 Dual Data Link Controller. The ML145488 is a two–channel ISDN LAPD controller with an on–chip direct memory access DMA controller. It is intended for ISDN

Contextual Info: D M A C O N TR O LLE R 8.1 AMDÌ1 O V E R V IE W Direct memory access DMA permits the transfer of data between memory and peripherals without CPU involvement. With DMA transfers, the DMA controller becomes the bus master. The arbitration for the bus is internal to the processor and is not visible externally. When

Intel 8237A

Abstract: intel 8237A DMA Controller 82C37A A8237
Contextual Info: a8237 Programmable DMA Controller April 1999, ver. 1.01 Features Data Sheet • ■ ■ ■ ■ ■ ■ General Description a8237 MegaCore function implementing a programmable direct memory access DMA controller Optimized for FLEX® architecture Provides four independent channels

EP660

Contextual Info: Eureka Technology EP660 DMA Controller FEATURES • Multiple independent DMA modules • Up to 16 DMA channels supported • Designed for ASIC or FPGA implementations in various system environments • Two types of DMA modules for memory memory and memory - I/O data transfer.

CRC-16

Abstract: Z16C35 sdlc ibm signals SDLC synchronous signals
Contextual Info: Z16C35 Z16C35 CMOS ISCC INTEGRATED SERIAL COMMUNICATIONS CONTROLLER GENERAL DESCRIPTION The Z16C35 ISCC™ is a CMOS Superintegrated device with a flexible Bus Interface Unit BIU connecting a builtin Direct Memory Access (DMA) cell to the CMOS Serial

Contextual Info: M H I H Galileo "SmsI Technology, Inc. » System Controller GT- 32090 For ¡960JX Processors _ , . _ Preliminary, Rev. 2.0 FEATURES Integrated system controller for embedded applica­ tions Supports the ¡960JX family of CPUs 16-33MHz bus frequency Flexible DRAM controller

M82C54

Abstract: i386 SL 82380 i386 Engine intel 82380 M80386 82380 INTEGRATED SYSTEM PERIPHERAL i386 ex K12 (1 GATE) INTEL i386 pipeline architecture
Contextual Info: M82380 HIGH PERFORMANCE 32-BIT DMA CONTROLLER WITH INTEGRATED SYSTEM SUPPORT PERIPHERALS Y Y Y High Performance 32-Bit DMA Controller 40 Mbytes sec Maximum Data Transfer Rate at 20 MHz 8 Independently Programmable Channels Y i386 TM Processor Shutdown Detect and

GT-32090

Abstract: AD2699 PCMCIA SRAM Card MON960 QS3257 ad2690
Contextual Info: System Controller Galileo For i960JX Processors Technology, Inc. GT- 32090 Preliminary, Rev. 2.0 March 1996 NOTE: Always contact Galileo Technology for possible updates before starting a design. FEATURES • Integrated system controller for embedded applications

processor cross reference

Abstract: DATASHEET OF DMA dma controller ADSP-21065 ADSP-21065L CHN 643 CHN 632 CHN 617 CHN 616 CHN 642
Contextual Info:  '0$ Figure 6-0. Listing 6-0. Table 6-0. Table 6-0. Direct Memory Access DMA provides a mechanism for transferring an entire block of data. The processor’s on-chip DMA controller relieves the core processor of moving data between internal memory and an external data source or

DSP56300

Abstract: DSP56301 TX01
Contextual Info: Freescale Semiconductor, Inc. Freescale Semiconductor Freescale Semiconductor, Inc. APR23/D Using the DSP56300 Direct Memory Access Controller Freescale Semiconductor, Inc., 2004. All rights reserved. For More Information On This Product, Go to: www.freescale.com

design of dma controller using vhdl

Abstract: FPGA based dma controller using vhdl timing diagram of DMA Transfer CY39100V676-200MBC
Contextual Info: Microprocessor Peripherals FPGA/CPLD IP Inventra DMAx1-B1 DMA Controller FISPbus INTERFACE DMA_END DMA A REGISTER INTERFACE FISPbus INTERFACE D FTS FTR DMAx1-B1 IR 2 DMA B SYSTEM DMA_REQ A S H E E T DMAx1-B1 key features: • Single-channel DMA controller with

ISP2312

Abstract: ISP2300 PC99 QLOGIC 388-PIN
Contextual Info:  Simplify ISP2312 Data Sheet Dual 2-Gb Fibre Channel to 133-MHz PCI-X Controller The ISP2312 is a highly integrated single-chip, dual-channel, bus master, Fibre Channel processor that targets storage, clustering, and networking applications. This chip connects a conventional PCI

Contextual Info: ß fö H O M O K lM lf intei M82380 HIGH PERFORMANCE 32-BIT DMA CONTROLLER WITH INTEGRATED SYSTEM SUPPORT PERIPHERALS High Performance 32-Bit DMA Controller — 40 MBytes/sec Maximum Data Transfer Rate at 20 MHz — 8 Independently Programmable Channels DRAM Refresh Controller