TTL28 Search Results

diode s1 77

Abstract: S124 diode s1 diode s1 74 socket s1 S1-100 S1-128
Contextual Info: P1 TTL0 P1 D3 A1 TTL3 A2 TTL6 A3 TTL9 A4 D2 D1 D0 S1-118 S1-110 S1-103 S1-100 TTL1 TTL8 C3 B4 TTL11 C4 TTL13 C5 TTL15 C6 TTL16 C7 TTL17 C8 TTL19 C9 AGND C10 PVCC C11 TTL20 C12 TTL21 C13 TTL22 C14 TTL23 C15 TTL24 C16 TTL25 C17 PVCC C18 TTL26 C19 PVPP C20 TTL28

CS 5211

Abstract: XC1704 U2A18 A1529 ALI M16 ID99 b21 a03 aO d07 S234 TTL-45
Contextual Info: A [00:1B] P1 P1 P1 S1-37 AOO TTLO A1 TTL3 A2 51-5 TMS 52-11 CEO TTL1 B1 DV TTL4 B2 D05 D02 51-21 TTL7 B3 5 2- 27 TTL10 B4 A5 51-40 TTL12 B5 AID5 A6 52-2 T T L14 B6 AID4 A7 PVCC B7 AIDO A8 +5V B8 TTL6 A3 TTL9 A4 AID6 AID1 DATA DO See note 5. A9 A 10 AID3 A ll

SSFXLDM-TTL-50G

Abstract: SSFXLDM-TTL-90T
Contextual Info: ta□ E D ENGINEERED • 3333203 Q0Q07ÛS TL3 EGC COMPONENTS C C O M P A T IB L E -TAP O G IC MODULE T2L input and outputs Delays stable and precise 14-pin Space Saver package Leads - thru-hole, J, Gull Wing or Tucked # Available in delays from 15 to 1000ns

FXLDM-TTL-50G

Abstract: FXLDM-TTL-70J FXLDM-TTL-80F FXLDM-TTL-90T rf delay line 45X2 FXLDM-TTL-1000 X7250
Contextual Info: Cozv profile t 2l C O M P A T IB L E „ A 10-TAP LOGIC DELAY MODULE T2L input and outputs Delays stable and precise 8-pin DIP package Leads - thru-hole, J, Gull Wing or Tucked Available in delays from 10 to 500ns # Output and four 4 taps - each isolated and with 10 T2 L fan-out capacity

diode t25 4 B9

Abstract: transistor af18 socket s1 diode t25 4 d9
Contextual Info: P1 TTL0 D3 A1 TTL3 A2 TTL6 A3 TTL9 P1 D2 D1 D0 A4 S1-W2 S1-AA4 S1-AD3 S1-AE3 TTL1 P1 D4 B1 TTL4 B2 TTL7 B3 TTL10 B4 AID6 A5 TTL12 B5 AID5 A6 TTL14 B6 AID4 A7 PVCC B7 AID0 A8 +5V B8 AID1 A9 TTL18 B9 AID2 A10 AGND B10 AID3 A11 TTL44 B11 S1-U2 S1-R2 D6 TDI TTL2

HW-133-PC68

Abstract: HW-133 S124 socket s1 S1-25 s159 socket s1 a1 a2 61S161 XC7354 MRX TTL-45
Contextual Info: ZONE REV 01 P1 TTL0 TTL3 A2 TTL6 A3 TTL9 A4 AID6 AID5 D3/D0 D2/D4 S1-25 S1-29 S1-28 S1-27 TTL1 B2 TTL7 B3 TTL10 B4 A5 TTL12 B5 A6 TTL14 B6 D1/D3 D0/D2 AID4 A7 PVCC B7 AID0 A8 +5V B8 A9 AID2 AID3 TTL18 B9 A10 AGND B10 A11 TTL44 B11 AID7 A12 AGND B12 AGND A13

S124

Abstract: diode s1 85
Contextual Info: P1 TTL0 P1 D3 A1 TTL3 A2 TTL6 A3 TTL9 A4 D2 D1 D0 S1-57 S1-54 S1-52 S1-51 TTL1 TTL4 B2 TTL7 B3 TTL10 B4 A5 TTL12 B5 AID5 A6 TTL14 B6 AID4 A7 PVCC B7 AID0 A8 PVSP B8 AID1 A9 TTL18 B9 AID2 A10 AGND B10 AID3 A11 TTL44 B11 AID7 A12 AGND B12 AGND A13 AGND B13 CGND

HW-133

Abstract: HW-133-PQ44 S124 XC7354 S1-11 XC7354 MRX TTL-45 aid-1
Contextual Info: ZONE REV 01 P1 TTL0 TTL3 A2 TTL6 A3 TTL9 A4 AID6 INITIAL RELEASE PER DCN #6790 P1 D3 A1 D2 CE D1 (OE) S1-11 S1-14 S1-13 S1-12 TTL1 B1 TTL4 B2 D4 (DATA) S1-16 S1-19 D6 TTL2 C1 TTL5 C2 TTL7 B3 TTL8 C3 B4 TTL11 C4 A5 TTL12 B5 TTL13 C5 AID5 A6 TTL14 B6 TTL15

socket s1

Abstract: diode s1 61 diode s1 77 diode s1 85 S124 040 d10 diode s1 diode s1 74 HW-133-PQ160 S1 18
Contextual Info: P1 TTL0 P1 D3 A1 TTL3 A2 TTL6 A3 TTL9 A4 D2 D1 D0 S1-90 S1-82 S1-79 S1-77 TTL1 TTL4 B2 TTL7 B3 TTL10 B4 A5 TTL12 B5 AID5 A6 TTL14 B6 AID4 A7 PVCC B7 AID0 A8 PVSP B8 AID1 A9 TTL18 B9 AID2 A10 AGND B10 AID3 A11 TTL44 B11 AID7 A12 AGND B12 AGND A13 AGND B13 CGND

diode b27

Abstract: diode b26 TTL20 S124 diode b29 socket s1 53 S1 TTL-45
Contextual Info: ZONE REV 01 DATE REVISION DESCRIPTION INITIAL RELEASE PER DCN #6875 DRAWN 5/23/95 CHECK EWR APPVD CH FE Further Revision history is available on Matrix. P1 TTL0 A1 TTL3 A2 TTL6 A3 TTL9 A4 AID6 P1 D3 D2 D1 S1-7 S1-8 S1-9 S1-10 TTL1 P1 D4 B1 TTL4 B2 S1-63 S1-61

MARKING 25J

Abstract: Manufacturer Logos
Contextual Info: ENGINEERED COMPONENTS CO 3flE D 33332Ô3 □DD07Sb t> H E 6 C T- ¥5-07 lowprofile t 2l COMPATIBLE DIP DIGITAL FREOUENCY MULTIPLIER MODULE M ìnì # T^L input and output % Output wavetrain synchronized with input square wave # 8-pin DIP package # Available in frequencies from 2 Mhz to

synchronous inverter schematic ims 1600

Abstract: elcot tv kit circuit diagram iosq 050 pin diagram for IC cd 1619 cp in fm smd code transistor sd IL44 Z ET 439 IL44 transistor ksv3100a UTM ceramic RESISTOR 390 210-9
Contextual Info: CONFIGURABLE DESIGN PLD 1 S i 2 0 Regan Brampton, Tel: (4 1 6 Fax: (4 1 6 ) 9 • Si APPLICATION BOOK F P GA 9 LOGIC 4 Ì 4(I M A S S O C IA T E S Road, Unit 14 O ntario L 7 A 1C3 8 4 0 -6 0 6 6 8 4 0 -6 0 9 1 • GATE A R R A Y 1 9 9 5 iilmËL Atmel Programmable Logic Devices (PLDs)

XC95108XL

Abstract: si122 ISA-96 HW-133 RH A4 130 XC95144XL IS9B TTL-45 SI-122
Contextual Info: P1 P1 TTLO TTL3 TTL6 TTL9 AID6 AID5 _Q3_ A1 A2 A3 A4 5 1-B O _Q2_ 5 1 -7 4 DI 5 1 -7 1 _BD_ S I— 69 TT L1 TTL4 TTL7 TTL10 GND A5 TTL12 A6 TTL14 P1 5 1 -8 2 TTL2 5 1 -8 7 TTL5 C2 B3 TTL8 C3 B4 TTL11 C4 B7 AI DO A8 +5V B8 AID1 A9 TTL18 B9 AID3 AID7 All TTL44

9536XL

Abstract: HW-133 HW-133-VQ64 A2 5160 64-pin VQFP xc9572xl TTL-45 ISA-96
Contextual Info: A1 D3ÍA11 A2 D2 A1D) A3 Dlf A9Ì TTL9 A4 DO(AB) AID6 A5 TTLO TTL3 TTL6 P1 P1 P1 S I—24S1-22 GND B2 D6(D1) S1-35 TTL5 C2 B3 TTL8 C3 TTL10 B4 TTL11 C4 TTL12 B5 TTL13 C5 TTL15 C6 TTL16 C7 T TL7 S I—19 D4ÍA12) TTL2 T T L4 S1-20 B1 S1-25 TTL1 AID5 A6 TTL14

Contextual Info: Cozi> p r o f i t t 2l COMPATIBLE Mini DIP FREQUENCY ER MODULE # T2L FAST input and outputs # Output wavetrain synchronized with input square wave # 8-pin DIP package The MDFDFMM-TTL is offered in thirty-eight 38 standard clock frequencies from 2 MHz to 100 MHz. When tested under the "Test

S124

Contextual Info: P1 TTL0 P1 D3 A1 TTL3 A2 TTL6 A3 TTL9 A4 AID6 D2 D1 S1-31 S1-33 S1-36 S1-37 TTL1 P1 D4 B1 TTL4 B2 S1-30 S1-27 D6 TTL2 C1 TTL5 C2 TTL7 B3 TTL8 C3 TTL10 B4 TTL11 C4 A5 TTL12 B5 TTL13 C5 AID5 A6 TTL14 B6 TTL15 C6 AID4 A7 PVCC B7 TTL16 C7 AID0 A8 +5V B8 TTL17

SO8 DIP8 socket

Abstract: DIP8 socket HW-137-DIP8 bin to hex TTL-30 TTL-45 dead bug socket A21 SO8
Contextual Info: ZONE P1 REV 01 INITIAL RELEASE PER DCN #6629 3/27/95 02 CHANGED PER DCN #7044 6/27/95 03 CHANGED PER DCN #0100160 11/04/96 P1 A1 TTL1 B1 TTL2 C1 TTL3 A2 TTL4 B2 TTL5 C2 TTL6 A3 TTL9 A4 AID6 S1-14, S2-6, S3-6 S1-2, S2-1, S3-1 TTL7 B3 TTL8 C3 TTL10 B4 TTL11

S124

Abstract: diode s1 74 s167 TTL-45 HW-133 S176
Contextual Info: ZONE REV 01 P1 TTL0 TTL3 A2 TTL6 A3 TTL9 A4 AID6 A5 D3 D2 D1 D0 S1-36 S1-33 S1-32 S1-31 TTL1 TTL4 B2 C3 C4 TTL12 B5 TTL13 C5 TTL15 C6 TTL16 C7 TTL17 C8 TTL19 C9 AGND C10 PVCC C11 PVCC B7 A8 +5V B8 AID1 A9 TTL18 B9 AID2 A10 AGND B10 AID3 A11 TTL44 B11 AID7

diode s1 77

Abstract: ttl26 S1-11 s176 S183 TTL-45 ISA-84
Contextual Info: ZONE REV 01 P1 TTL0 TTL3 A2 TTL6 A3 TTL9 A4 AID6 INITIAL RELEASE PER DCN #6873 P1 D3 A1 D2 D1 S1-9 S1-10 S1-11 S1-12 TTL1 B2 D4 S1-77 S1-75 D6 TTL2 C1 TTL5 C2 TTL7 B3 TTL8 C3 TTL10 B4 TTL11 C4 A5 TTL12 B5 TTL13 C5 AID5 A6 TTL14 B6 TTL15 C6 AID4 A7 PVCC B7

S1A14

Abstract: S1d9 225-pin BGA Socket S1g4 XC73108 S1-K14 S1G15 HW-133 S1D5 S1D-13
Contextual Info: ZONE REV 01 P1 TTL0 TTL3 A2 TTL6 A3 TTL9 A4 AID6 D3 D2 D1 D0 S1-M15 S1-N14 S1-P14 S1-N12 A5 TTL1 B2 TTL7 B3 TTL10 B4 TTL12 A6 TTL14 B6 AID4 A7 PVCC B7 AID0 A8 PVSP B8 AID1 A9 TTL18 B9 AID2 A10 AGND B10 AID3 A11 TTL44 B11 AID7 A12 AGND B12 AGND A13 AGND B13

Socket S1g4

Abstract: ISA-96 Socket S1g2 mpg 1010 Socket S1g3 Socket S1g1 XC9536 XC9536XL TTL-30 TTL-45
Contextual Info: P1 P1 D 3/TD I P1 TTL2 C1 S1-D2 TTL5 C2 S1-E2 TTL8 C3 TT L 10 < TTL11 C4 TT L 12 <s T T L 13 . C5 TTL14 B5 <s B6 TTL15 . C6 A7 P VC C <v TTL16 C7 AIDO A8 +5V <s AID1 A9 TT L 18 TTLO A1 S1-B3 TTL1 <s S1-C3 TTL3 • A2 S1-C2 T T L 4 <s S1-E1 TTL6 • A3 S1-B1

74ALS283

Abstract: 74ALS148 74ALS194 0-99 counter by using 4 dual jk flip flop 004887 ATL60 TTL109 TTL138 TTL139 TTL148
Contextual Info: Cell Library Index How to Use This Cell Library Index The cell index contains the macro cell’s timing, size and loading information. The data included in the cell timing information is explained in detail below. Cell Parameters Sites: Lists the number of gate array cell sites the macrocell occupies. This can be

ssf 7510

Abstract: SSFXLDM-TTL-50G SSFXLDM-TTL-80F SSFXLDM-TTL-90T
Contextual Info: B L O C K D IA G R A M IS S H O W N B E L O W M E C H A N IC A L D E T A IL IS S H O W N B E L O W V cc 14 .800 14 13 12 11 10 9 P in No. Pin No. V 2 ^ SSFXLDM- 4 IN 1 1 2 6 8 OUT 3 5 7 9 C 3 4 5 6 7 TAP 2 13 TA P 4 12 TAP 6 11 TAP 0 10 OUT il; m f t f r D E LA Y LIN E W IT H

Contextual Info: ENGINEERED C O M P O N E N T S C bOE D •I 3 3 3 3 2 A 3 OOOOflCH 227 WÊ EGC Cozv -profite T*L COMPATIBLE 10-TAP OCIC MODULE T2L input and outputs Delays stable and precise 14-pin DIP package time is measured at the +1 .5V level on the leading edge. Rise