TTL22 Search Results

diode s1 77

Abstract: S124 diode s1 diode s1 74 socket s1 S1-100 S1-128
Contextual Info: P1 TTL0 P1 D3 A1 TTL3 A2 TTL6 A3 TTL9 A4 D2 D1 D0 S1-118 S1-110 S1-103 S1-100 TTL1 TTL8 C3 B4 TTL11 C4 TTL13 C5 TTL15 C6 TTL16 C7 TTL17 C8 TTL19 C9 AGND C10 PVCC C11 TTL20 C12 TTL21 C13 TTL22 C14 TTL23 C15 TTL24 C16 TTL25 C17 PVCC C18 TTL26 C19 PVPP C20 TTL28

CS 5211

Abstract: XC1704 U2A18 A1529 ALI M16 ID99 b21 a03 aO d07 S234 TTL-45
Contextual Info: A [00:1B] P1 P1 P1 S1-37 AOO TTLO A1 TTL3 A2 51-5 TMS 52-11 CEO TTL1 B1 DV TTL4 B2 D05 D02 51-21 TTL7 B3 5 2- 27 TTL10 B4 A5 51-40 TTL12 B5 AID5 A6 52-2 T T L14 B6 AID4 A7 PVCC B7 AIDO A8 +5V B8 TTL6 A3 TTL9 A4 AID6 AID1 DATA DO See note 5. A9 A 10 AID3 A ll

MI b11

Abstract: A241 ISA-96 TTL-45
Contextual Info: TTLO TTL3 T TL6 T TL9 AID6 P1 P1 P1 DATA2 A1 DATAI A2 CEO A3 DATAD A4 S I —6 TTL1 S I —16 TTL4 51—13 TTL7 51-1 TTL10 A5 TTL12 TTL2 C1 DATA4 S I —14- TTL5 C2 DATA6 B3 TTL8 C3 B4 TTL11 C4 B2 A6 TTL14 B6 AID4 A7 PVCC B7 AIDO A8 +5V B8 AID1 A9 TTL18 B9

Contextual Info: T - Technical Data. CD54/74HC7266 Filé Number M3Q2571 G01Ô007 27E J> H A RR IS SE MI C O N D SE CT OR 1780 T BHAS High-Speed CMOS Logic Quad 2-Input Exclusive-NOR Gate # > æ > Type Features: • Four independent Exclusive-N O R ■ Buffered inputs and outputs

CD74HC7266

Abstract: CD74HC7266E CD74HC7266M HC7266 TTL226
Contextual Info: [ /Title CD74H C7266 /Subject (High Speed CMOS Logic Quad 2Input EXCLUSIVE CD74HC7266 Data sheet acquired from Harris Semiconductor SCHS219 High Speed CMOS Logic Quad 2-Input EXCLUSIVE NOR Gate August 1997 Features Description • Four Independent EXCLUSIVE NOR Gates

TL300

Abstract: TL65
Contextual Info: tozu -profile t 2l C O M P A T IB L E Mini Dl LO G IC DELAY DULE _ f # T2L Input and outputs all m odules is 4ns m axim um w hen m easured from 0.8V to # Delays stable and precise 2.0V . T e m p e ra tu re co e fficie n t o f delay is approxim ately +500

Contextual Info: Cow profite > 1 C ^ t 2l CO M PATIBLE A lAP* PIXEL CLOCK GENERATOR MODULE j # T^L FAST input and output # Output wavetrain can be synchronized with random events # 20-pin DIP package .290 high # Available in frequencies from 2MHz to 30MHz # Output frequencies controlled to within ±2%

Contextual Info: [ /Title CD74H C7266 /Subject (High Speed CMOS Logic Quad 2Input EXCLUSIVE CD54HC7266, CD74HC7266 Data sheet acquired from Harris Semiconductor SCHS219D High-Speed CMOS Logic Quad 2-Input EXCLUSIVE NOR Gate August 1997 - Revised September 2003 Features Description

Contextual Info: [ /Title CD74H C7266 /Subject (High Speed CMOS Logic Quad 2Input EXCLUSIVE CD54HC7266, CD74HC7266 Data sheet acquired from Harris Semiconductor SCHS219D High-Speed CMOS Logic Quad 2-Input EXCLUSIVE NOR Gate August 1997 - Revised September 2003 Features Description

CD54HC7266

Abstract: CD54HC7266F3A CD74HC7266 CD74HC7266E CD74HC7266M CD74HC7266MT HC7266 TTL226
Contextual Info: [ /Title CD74H C7266 /Subject (High Speed CMOS Logic Quad 2Input EXCLUSIVE CD54HC7266, CD74HC7266 Data sheet acquired from Harris Semiconductor SCHS219D High-Speed CMOS Logic Quad 2-Input EXCLUSIVE NOR Gate August 1997 - Revised September 2003 Features Description

TTL226

Abstract: CD54HC7266 CD54HC7266F3A CD74HC7266 CD74HC7266E CD74HC7266M CD74HC7266M96 HC7266
Contextual Info: [ /Title CD74H C7266 /Subject (High Speed CMOS Logic Quad 2Input EXCLUSIVE CD54HC7266, CD74HC7266 Data sheet acquired from Harris Semiconductor SCHS219B High-Speed CMOS Logic Quad 2-Input EXCLUSIVE NOR Gate August 1997 - Revised May 2003 Features Description

CD54HC7266

Abstract: CD54HC7266F3A CD74HC7266 CD74HC7266E CD74HC7266M CD74HC7266MT HC7266 TTL226
Contextual Info: [ /Title CD74H C7266 /Subject (High Speed CMOS Logic Quad 2Input EXCLUSIVE CD54HC7266, CD74HC7266 Data sheet acquired from Harris Semiconductor SCHS219D High-Speed CMOS Logic Quad 2-Input EXCLUSIVE NOR Gate August 1997 - Revised September 2003 Features Description

Contextual Info: surface mount t 2l CO M PATIBLE Wee DIP M U LTI-LO G IC J DELAY LINE # T2 L FAST input and outputs # Delays stable and precise # SO-14 pin pattern # Wee DIP package .235 high # Available in delays from 5 to 250ns — each isolated and with 10 T2L fan-out capacity

Socket S1g1

Abstract: HW-133 XC95144XL S1A13 TTL32 s1d1 TTL-45 s1n6 S1-N13
Contextual Info: A1 D3 TTL3 A2 _D2_ T TL6 A3 T TL9 A4 TTLO AID6 AID5 51—A 1 P1 P1 TTL1 S1-M 13 TTL4 51—NI Z TTL7 S1-H11 TTL10 GND TTL12 A6 TTL14 B1 B6 TCK VCC A8 +5V B8 AID1 A9 TTL18 B9 AID7 A ll TTL44 A 12 AGND A 13 CGND A14 AGND MOUNTI NG HOLES B12 B16 S1-E11 B17 AGND

HW-133-PC68

Abstract: HW-133 S124 socket s1 S1-25 s159 socket s1 a1 a2 61S161 XC7354 MRX TTL-45
Contextual Info: ZONE REV 01 P1 TTL0 TTL3 A2 TTL6 A3 TTL9 A4 AID6 AID5 D3/D0 D2/D4 S1-25 S1-29 S1-28 S1-27 TTL1 B2 TTL7 B3 TTL10 B4 A5 TTL12 B5 A6 TTL14 B6 D1/D3 D0/D2 AID4 A7 PVCC B7 AID0 A8 +5V B8 A9 AID2 AID3 TTL18 B9 A10 AGND B10 A11 TTL44 B11 AID7 A12 AGND B12 AGND A13

S124

Abstract: diode s1 85
Contextual Info: P1 TTL0 P1 D3 A1 TTL3 A2 TTL6 A3 TTL9 A4 D2 D1 D0 S1-57 S1-54 S1-52 S1-51 TTL1 TTL4 B2 TTL7 B3 TTL10 B4 A5 TTL12 B5 AID5 A6 TTL14 B6 AID4 A7 PVCC B7 AID0 A8 PVSP B8 AID1 A9 TTL18 B9 AID2 A10 AGND B10 AID3 A11 TTL44 B11 AID7 A12 AGND B12 AGND A13 AGND B13 CGND

HW-133

Abstract: HW-133-PQ44 S124 XC7354 S1-11 XC7354 MRX TTL-45 aid-1
Contextual Info: ZONE REV 01 P1 TTL0 TTL3 A2 TTL6 A3 TTL9 A4 AID6 INITIAL RELEASE PER DCN #6790 P1 D3 A1 D2 CE D1 (OE) S1-11 S1-14 S1-13 S1-12 TTL1 B1 TTL4 B2 D4 (DATA) S1-16 S1-19 D6 TTL2 C1 TTL5 C2 TTL7 B3 TTL8 C3 B4 TTL11 C4 A5 TTL12 B5 TTL13 C5 AID5 A6 TTL14 B6 TTL15

socket s1

Abstract: diode s1 61 diode s1 77 diode s1 85 S124 040 d10 diode s1 diode s1 74 HW-133-PQ160 S1 18
Contextual Info: P1 TTL0 P1 D3 A1 TTL3 A2 TTL6 A3 TTL9 A4 D2 D1 D0 S1-90 S1-82 S1-79 S1-77 TTL1 TTL4 B2 TTL7 B3 TTL10 B4 A5 TTL12 B5 AID5 A6 TTL14 B6 AID4 A7 PVCC B7 AID0 A8 PVSP B8 AID1 A9 TTL18 B9 AID2 A10 AGND B10 AID3 A11 TTL44 B11 AID7 A12 AGND B12 AGND A13 AGND B13 CGND

diode b27

Abstract: diode b26 TTL20 S124 diode b29 socket s1 53 S1 TTL-45
Contextual Info: ZONE REV 01 DATE REVISION DESCRIPTION INITIAL RELEASE PER DCN #6875 DRAWN 5/23/95 CHECK EWR APPVD CH FE Further Revision history is available on Matrix. P1 TTL0 A1 TTL3 A2 TTL6 A3 TTL9 A4 AID6 P1 D3 D2 D1 S1-7 S1-8 S1-9 S1-10 TTL1 P1 D4 B1 TTL4 B2 S1-63 S1-61

MARKING 25J

Abstract: Manufacturer Logos
Contextual Info: ENGINEERED COMPONENTS CO 3flE D 33332Ô3 □DD07Sb t> H E 6 C T- ¥5-07 lowprofile t 2l COMPATIBLE DIP DIGITAL FREOUENCY MULTIPLIER MODULE M ìnì # T^L input and output % Output wavetrain synchronized with input square wave # 8-pin DIP package # Available in frequencies from 2 Mhz to

Contextual Info: High-Reliability High-Speed CMOS Logic ICs _ CD54HC7266/3A Quad Exclusive NOR 1A — - The RCA CD54HC7266 contains fou r independent EXCLUSIVE-NOR gates in one package. They provide the system designer w ith a means fo r im plem entation of the

jj-01

Contextual Info: toio profite t 2l CO M PA TIBLE ^ K o c ic DELAY M O DU LE J T 2L Input and outputs m o d u le s is 4 n s m a x im u m w h e n m e a s u re d fro m 0 .8 V to 2.0V. Delays stable and precise T e m p e ra tu re c o e ffic ie n t o f d e la y is a p p ro x im a te ly + 5 0 0 p p m /

Contextual Info: [ /Title CD74H C7266 /Subject (High Speed CMOS Logic Quad 2Input EXCLUSIVE CD54HC7266, CD74HC7266 Data sheet acquired from Harris Semiconductor SCHS219D High-Speed CMOS Logic Quad 2-Input EXCLUSIVE NOR Gate August 1997 - Revised September 2003 Features Description

4000 series CMOS Logic ICs

Abstract: SCLA007A 74HC04 fan out sn74 series TTL logic gates list HC4040 application note schematic thyristor based inverter 74hc family Difference between LS, HC, HCT devices HC165 cmos 4000
Contextual Info: HCMOS Design Considerations SCLA007A September 2002 1 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries TI reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services