TTL IC 74 Search Results

dtl logic gates

Abstract: ttl NAND gate circuit series inverter circuit diagrams 9000 ttl 930 series dtl ttl NAND gate with expander K 9008 TTL 7430 6 a 8 mic 4 pin mic circuit
Contextual Info: Logic Integrateci Circuits, MIC 9 0 0 0 Series TTL C irc u it F unctions Compatible w ith M IC 930 Series DTL and other TTL and DTL Series M IC M IC M IC M IC M IC M IC M IC M IC M IC M IC M IC M IC M IC 9000 9001 9002 9003 9004 9005 9006 9007 9008 9009 9012

7400 fan-out

Abstract: 7402 nor 7491 8-bit 7490 Decade Counter TTL 7400 TTL 7400 AND propagation delay TTL 7400 propagation delay TTL 7475 TTL 7490 7402 J-K Flip-Flop
Contextual Info: Logic Integrateci Circuits, MIC 7400 Series TTL G a te s in order of gates per package Type M IC M IC M IC M IC M IC M IC M IC M IC M IC M IC M IC M IC 7430 7453 7454 7420 7440 7450 7451 7460 7410 7400 7401 7402 Positive logic definition Gates per package

7400 series

Abstract: TTL 7400 quad 2 input standard ttl nand gate 7400 pin configuration 7400 7400 NAND Gate 2 input 7400 2-input nand gate jk 7400 ttl nand gate 7400 quad ttl nand gate 7400
Contextual Info: Logic Integrated Circuits, MIC 7400 Series TTL C ir c u it F u n c tio n s A fu lly com patible ceramic packaged 7400 Series w ith in pu t clam ping diodes. Excellent com patibility w ith M IC 9 3 0 -R Series DTL. M IC M IC M IC M IC M IC M IC M IC M IC M IC

Contextual Info: Digitally Programmable data delay Delay Units SERIES: PDU-1316 devicesYinc. 4-Bit TTL Interfaced Specifications: Test Conditions: • ■ ■ ■ Input signal requirement: TTL logic Output fan-out: TTL s ch o ttky loads Delay variation: M on o to n ic in one d irection

PO74G74

Abstract: TTL 74-series IC LIST PO74G04 PO74G2305A PO74G04A IC Quad 3-input Positive-OR gates 49FCT32807 FSAV332 FSAV450 TSSOP 16 Package
Contextual Info: Cross Reference / Pin to Pin & Package to Package Compatible IC List Standard 1.65V -3.6 V TTL / CMOS Clock Buffer PotatoSemi Package Pericom IDT PO74G38072A 1GHz 1 to 2 TTL SOIC 8 74FCT38072 PO74G38074A 900MHz 1 to 4 SOIC 8 74FCT38074 PO74G304A 700MHz 1 to 4

PDU-1316

Abstract: 131645
Contextual Info: data Digitally Programmable delay NS Delay Units SERIES: PDU-1316 devices* 4-Bit TTL Interfaced Specifications: Test Conditions: • ■ ■ ■ Input signal requirem ent: TTL logic. Output fan-out: TTL S ch o ttky loads. Delay variation: M on o to n ic in one direction.

Contextual Info: « 9-BIT TTL-TO-ECL WITH TTL, ECL ENABLE SYNERGY SY10H600 SY100H600 S E M IC O N D U C T O R FEATURES DESCRIPTION • 9-bit ideal for byte-parity applications ■ Flow-through configuration ■ Extra TTL and ECL power/ground pins to minimize switching noise

74HC

Abstract: ELM7SU04BW
Contextual Info: CMOS LOGIC IC ELM7SU04BW Unbuffer Inverterx2 •General description ELM7SU04BW is CMOS unbuffer inverter IC includes 2 circuits IC. It realizes high speed operation similar to LS-TTL with lower power consumption by CMOS features. ■Features ・ Same electrical characteristic as 74HC series output current is around 1/2 of 74HC series

Contextual Info: *SYNERGY SINGLE SUPPLY QUAD PECL-TO-TTL WITH OUTPUT ENABLE S E M IC O N D U C T O R DESCRIPTION FEATURES • Translates positive ECL to TTL PECL-to-TTL ■ 300ps pin-to-pin skew ■ 500ps part-to-part skew ■ Differential internal design for increased noise

Contextual Info: S E M IC O N D U C T O R tm 74F132 Quad 2-Input NAND Schmitt Trigger General Description The F132 contains four 2-input NAND gates which accept standard TTL input signals and provide standard TTL output levels. They are capable of transforming slowly changing in­

uA 741 IC pin configuration

Abstract: internal circuit diagram of IC 741 ic 741 datasheet internal diagram of 741 IC uA 741 OF IC 741 pin diagram of ic 741 uA 741 IC shift register ic pdf of 741 ic
Contextual Info: VITESSE SEMICONDUCTOR CORPORATION Preliminary Datasheet 500 Mb/s Video Shift Register IC VSC6424 Features • ECL and TTL I/Os: ECL for high-speed interface, TTL for low-speed interface • Multiplex or Demultiplex Operation • Selectable Shift Register Length

811Z

Contextual Info: * SING LE SUPPLY 1:9 SYNERGY Clockworks SY100S811 P EC L/TTL-TO -PECL S E M IC O N D U C T O R FEATURES DESCRIPTION PECL version of popular ECLinPS El 11 Low skew Guaranteed skew spec V bb output TTL enable input Selectable TTL or PECL clock input Single +5V supply

CY101E383

Abstract: diode SKE 39
Contextual Info: W r CY10E383 CY101E383 CYPRESS ECL/TTL/ECL Translator and High-Speed Bus Driver Features Functional Description • B iC M O S for optim um speed/power • H igh speed max. — 2.5 n s Ipu TTL-to-EC L — 3.5 n s tpo EC L-to-TTL The CY10/101E383 is a new-generation

BD 9222

Abstract: SN7481 SN7484 SN7442 SN5481 WQ 5012 SN7444
Contextual Info: CIRCUIT TYPES SN5481, SN5484, SN7481, SN7484 16-BIT ACTIVE-ELEMENT MEMORIES TTL MSI SN5481/SN7481 CIRCUITS W FLAT PACKAGE TOP VIEW description The 16-bit active-element memory is a m o n o lith ic , high-speed, transistor-transistor-logic (TTL) X4 WRITE

Contextual Info: fax id: 5000 CY101E383 ECL/TTL/ECL Translator and High-Speed Bus Driver Featu res • B iC M O S for optimum speed/p ow er • High speed max. — 3.0 ns tpD TTL-to-ECL — 4 ns t PD ECL-to-TTL • Low skew < ± 1 ns • Can o perate on single +5V supply

M14A

Abstract: MM74C901 MM74C901M MM74C901N MM74C902 MM74C902M MM74C902N MS-011 N14A MM74C9010
Contextual Info: Revised January 1999 E M IC O N D U C T G R T M MM74C901 • MM74C902 Hex Inverting TTL Buffer • Hex N on-Inverting TTL Buffer General Description Features T he MM 74C901 and M M 74C 902 hex buffers em ploy com plem entary M OS to achieve w ide supply operating range,

Fairchild dtl catalog

Abstract: johnson and ring counter using ic 7495 equivalent of transistor 9014 NPN 4 bit bcd adder pin diagram and truth table using ic 7483 MIL-STD-806 alu 9308 d Fairchild 9300 NL940 Fairchild msi full subtractor circuit using ic 74153 multiplexer
Contextual Info: FAIRCHILD SEMICONDUCTOR THE TTL APPLICATIONS HANDBOOK THE TTL APPLICATIONS HANDBOOK Prepared by the Digital Applications Staff of Fairchild Semiconductor Edited by Peter Alfke and lb Larsen FAIRCHILD S E M IC O N D U C T O R 464 Ellis Street, M ountain View, California 94042

Contextual Info: CRYSTAL OSCILLATOR KSS E 1102-90041-AA5 1994.12 DATA SHEET V C X O [MODEL] VCXO-078B - 078& : TTL level crystal oscillator [FEATURES] ° "Small Size" as small as 1.9cc . 18.5 X 12.0X8.4 mm ° Using welded crystal. ° Hybrid-IC circuit construction. 0 TTL compatible output.

ELM7S04B

Abstract: 74HC INVERTER IC
Contextual Info: CMOS LOGIC IC ELM7S04B Inverter •General description ELM7S04B is CMOS inverter IC. It realizes high speed operation similar to LS-TTL with lower power consumption by CMOS features. The inner circuit structure of 3-stage logic gate obtains wider noise

ELM7S14B

Abstract: SCHMITT INVERTER ELM7S14 ELM7S14BEL 74HC
Contextual Info: CMOS LOGIC IC ELM7S14B Schmitt Inverter •General description ELM7S14B is CMOS schmitt inverter IC. It realizes high speed operation similar to LS-TTL with lower power consumption by CMOS features. The inner circuit structure of 3-stage logic gate obtains wider noise

ELM7S04

Abstract: elm7sxx 74HC ELM7S00 ELM7S02 ELM7S08 ELM7S32 ELM7S66 ELM7S86 ELM7SU04
Contextual Info: ELM7Sxx SERIES CMOS LOGIC IC • GENERAL DESCRIPTION ・ELM7S Series is a Silicon CMOS’s High-Speed Gate IC. It realizes High-Speed drive similar to LS-TTL with lower power consumption which CMOS features. Inner Circuit which consists of 3-phase composition

ttl nand gate

Abstract: B237 CD 5888 N74S04 transistor b143 e.s N74S00 ITT301 74s200 N74S00N N74S02N
Contextual Info: Signetics Integrated Circuits Schottky TTL Schottky TTL 74S Series Introduction S c h o ttk y T T L uses a d io d e cla m p design to ensure th e highest speed possible at T T L lo g ic levels ty p ic a lly 3ns gate p ro p a g a tio n de la y and 9 0 M H z f lip f lo p to g gle rate. H o w ever th e y rem ain c o m p a tib le w ith

Contextual Info: s e m ic o n d u c t o r Revised November 1999 100328 Low Power Octal ECL/TTL Bi-Directional Translator with Latch General Description Features The 100328 is an octal latched bi-directional translator designed to convert TTL logic levels to 100K ECL logic lev­

22AA

Abstract: H607 SY100H607 SY10H607 SY10H607JC HI 3520
Contextual Info: * SY10H607 SY100H607 REGISTERED HEX PECL-TO-TTL SYNERGY S E M IC O N D U C T O R DESCRIPTION FEATURES • Differential PECL data and clock inputs ■ 48mA sink, 15mA source TTL outputs ■ Single +5V power supply ■ Multiple power and ground pins to minimize noise