TTL 7202 Search Results

Contextual Info: QS7201, QS7202 Q High-Speed CMOS 5 1 2 x 9 , 1 Kx 9 FIFO Buffer Memories q¡ 7202 FEATURES • • • • • 12-ns flag and data access times Fully asynchronous read and write Zero fall-through time Expandable in depth with no speed loss TTL compatible input and output levels

TTL 7400

Abstract: transistor SI 6822 application notes signetics 74LS00 gate fairchild dtl pj 939 diode 7410 IC pj 939 lv bq 8050 ac servo controller schematic
Contextual Info: FAIRCHILD FAST' Applications Handbook A S chlum berger C om pany 1987 Fairchild Semiconductor Corporation, Digital Unit 333 Western Avenue, South Portland, Maine 04106 207/775-8700 TWX 710-221-1980 FAST Fairchild Advanced Schottky TTL is a registered trademark of

ISD 1720

Abstract: CYM1720
Contextual Info: CYM1720 p / CYPRESS Features • High-density 768-kilobit SRAM module • High-speed CMOS SRAMs — Access time of 15 ns • 56-pin, 0.5-inch-high ZIP package • Low active power — 1.8W max. for t\A = 25 ns • SMD technology • TTL-compatible inputs and outputs

7805 ACT

Abstract: FB 3306 ahct 367 Cmos 74 HC 1G14 ACT 4060 A Cross-Reference DATE CMOS 4060 cmos series HCT 138
Contextual Info: Section 3 Functional CrossĆReference 3 3–1 DEVICE BiCMOS ABT ALB ALVT BIPOLAR BCT LVT ALS AS F LS CMOS S TTL AC ACT AHC AHCT ’1G00 ✔ ✔ ’1G04 ✛ ✛ ’1GU04 ✛ ✛ ’1G08 ✔ ✔ ’1G14 ✛ ✛ ’1G32 ✔ ✔ ✔ ✔ ✔ ’02 ✔ ✔ ✔ ’03

9406A

Contextual Info: 9406 PROGRAM STACK FAIRCHILD TTL MACROLOGIC DESCRIPTIO N — The 9406 is a 16-word by 4 -b it "push-down po p-up" Program Stack. It is designed to im plem ent Program C ounter PC and return address storage fo r nested subroutines in programmable digital systems. The 9406 executes 4 instructions: Return,

P13V

Abstract: 9406
Contextual Info: 9406 PROGRAM STACK F A IR C H IL D TTL MACROLOGIC D E S C R IP T IO N — Th e 9406 is a 16-word by 4-bit "push-down pop-up" Program Stack. It is designed to implement Program Counter PC and return address storage for nested subroutines in programmable digital systems. The 9406 executes 4 instructions: R eturn,

valor pm

Contextual Info: High Efficiency Converters D C / D C Converters Schem atic Drawings Valor's series of DC/DC converters provide high conversion efficiency for PCM CIA and other LAN applications where power consumption is critical. Designed as upgrades of Valor's PM 7202 family of components, the

FB 3306

Abstract: 7200L 18504 845 motherboard circuit 7804 inverter 7805 ACT 845 motherboard BTL 8 236 CMOS 4060 cmos open collector
Contextual Info: Section 2 Functional Index Gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–3 Inverting/Noninverting Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–5 Buffers/Drivers and Bus Transceivers . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–5

8251a usart interface from z80

Abstract: UDL TM 500 f922 verilog code for 8254 timer l912 256x32 POWER MODULE TM 31 udl 500 78K3 F5S4
Contextual Info: L4E75BS DÜHBÖGb 3ÔÔ B I N E C E CB-C7, 5-VOLT 0.8-M ICRON CELL-BASED CMOS ASIC NEC NEC Electronics Inc. August 1993 Description Figure 1. Integrated HDD Solution with CBC7 Cell-Based ASIC with Embedded 78K3 MPU, Compiled SRAMs and A/D Converters CB-C7 cell-based product family is a 0.8-micron drawn

nec 2561 equivalent

Abstract: f bj04 TBA 931 765 floppy disk controller 78K3 L435 f305 F423 nec 2401 bg05
Contextual Info: CB-C7, 5-VOLT 0.8-MICRON CELL-BASED CMOS ASIC NEC Electronics Inc. August 1993 Description CB-C7 cell-based product family is a 0.8-micron drawn process with two- or three-layer metalization and is offered in 22 I/O pad ring step sizes. It is ideal for applications such

Fairchild ZN 1010

Abstract: GENERAL INSTRUMENT west 2500 ic ZN 415 FGE2000
Contextual Info: FGE Series ECL Gate Arrays PAIRCHIL.D A Schlum berc T'HO Qr>y 005596 January 1986 Description U/v\A m b The FGE Series of ECL gate arrays are the fastest silicon gate arrays com m ercially available. These advanced ECL gate arrays, ranging from 100 to 2840 equivalent gates, offer

Contextual Info: HIGH-SPEED EPI-CMOS 1024 X 9-BIT PARALLEL FIFO SPACE ELECTRONICS INC. SPACE PRODUCTS 7202ERP DATA INPUTS D0-D8 W 1 28 VCC D8 D4 D3 D5 D2 D6 D1 D7 D0 FL/RT SEi 7202ERP XI FF WRITE CONTROL RAM ARRAY 1024 X 9 WRITE POINTER EF XO/HF Q1 Q7 Q2 Q6 Q3 Q5 Q8 Q4 15

SN74HC02 Spice model

Abstract: philips semiconductor data handbook SDAD001C SDFD001B SCAD001D SN7497 spice model SN74AHC14 spice Transistor Crossreference SLLS210 ci ttl sn74ls00
Contextual Info: LOGIC OVERVIEW 1 FUNCTIONAL INDEX 2 FUNCTIONAL CROSSĆREFERENCE 3 DEVICE SELECTION GUIDE 4 3 LOGIC SELECTION GUIDE FIRST QUARTER 1997 IMPORTANT NOTICE Texas Instruments TI reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and advises its customers to obtain the latest

27C020-12

Abstract: 27PC020-12 LS020 A1025 LS020B 2097152-BIT
Contextual Info: TMS27C020 2097152-BIT UV ERASABLE PROGRAMMABLE TMS27PC020 2097152-BIT PROGRAMMABLE READ-ONLY MEMORY SM LS020B - N O V E M B E R 1990 - REVISED JU N E 1995 • Organization . . . 256K x 8 J PACKAGE TOP VIEW • Single 5-V Power Supply • Operationally Compatible With Existing

circuit diagram of rf transmitter and receiver

Abstract: circuit diagram video transmitter and receiver BCD-Decoder D24.3 Package high level block diagram for asynchronous FIFO long range transmitter receiver circuit diagram SEV 1011 ENCODER/CY7C9235 equalizer soic 14 foto transistor
Contextual Info: fax id: 5017 1CY 7B9 33 CY7B9234 CY7B9334 PRELIMINARY SMPTE HOTLink Transmitter/Receiver Features bler/Framer Controller CY7C9335 completing the four piece chipset to transfer uncompressed SMPTE-259M encoded data over high-speed serial links (fiber, coax, and twisted pair).

CY7B9234

Abstract: CY7B9334 CY7C9235 CY7C9335 4bit LFSR
Contextual Info: CY7B9234 CY7B9334 PRELIMINARY SMPTE HOTLink Transmitter/Receiver Features bler/Framer Controller CY7C9335 completing the four piece chipset to transfer uncompressed SMPTE-259M encoded data over high-speed serial links (fiber, coax, and twisted pair).

circuit diagram of rf transmitter and receiver

Abstract: foto sensor foto transistor long range transmitter receiver circuit diagram RF transmitter Receiver circuits CY7B933 fiber channel controller SEV 1011 Spec Lin Enterprise texas ttl data book
Contextual Info: fax id: 5004 1CY 7B9 33 CY7B923 CY7B933 HOTLink Transmitter/Receiver Features • • • • • • • • • • • • • • • • • • • that transfer data over high-speed serial links fiber, coax, and twisted pair . Standard HOTLink data rates range from

B9236

Abstract: CY7B933 STK*403-130 CY7B923 ECL100K
Contextual Info: CY7B923 CY7B933 HOTLink Transmitter/Receiver Features • • • • • • • • • • • • • • • • • • twisted pair . Standard HOTLink data rates range from 160-330 Mbits/second. Higher speed HOTLink is also available for high speed applications 160-400 Mbits/second), as

5d215

Abstract: CY7B9234 CY7B9334 CY7C9235 CY7C9335 B9234-19
Contextual Info: CY7B9234 CY7B9334 PRELIMINARY SMPTE HOTLink Transmitter/Receiver Features chipset to transfer uncompressed SMPTE-259M encoded video over high-speed serial links fiber, coax, and twisted pair . SMPTE HOTLink supports SMPTE-259M-BCD standard data rates at 177, 270, and 360 Mbps. Figure 1 illustrates typical

B9236

Abstract: ic B-923 CY7B923 CY7B933 ECL100K TOP SWITCH B-923 cypress cross reference B9237
Contextual Info: CY7B923 CY7B933 HOTLink Transmitter/Receiver Features • • • • • • • • • • • • • • • • • • Fibre-Channel-compliant IBM ESCON-compliant DVB-ASI-compliant ATM-compliant 8B/10B-coded or 10-bit unencoded Standard HOTLink: 160–330 Mbps

CY7B923

Abstract: CY7C42X5 CY7C924ADX
Contextual Info: 24ADXCY7 X CY7C924ADX 200-MBaud HOTLink Transceiver HOTLink devices are ideal for a variety of applications where parallel interfaces can be replaced with high-speed, point-topoint serial links. Some applications include interconnecting workstations, backplanes, servers, mass storage, and video

2 wheeler rr unit

Abstract: LSI CMOS GATE ARRAY
Contextual Info: FAIRCHILD A Schlumberger Company A y v ^ \ 005597 January 1986 Description 0 , J The FGC Series is an aavancea, high performance CMOS gate array family designed for LSI implementation of existing discrete logic systems and new designs requiring high density

B9237

Abstract: SA22-7202 utc D313 utc 317 B923-7
Contextual Info: CY7B923 CY7B933 5r C Y PR E SS HOTLink Transmitter/Receiver Features Functional Description • • • • • • • • • • The CY7B923 H O TLink Transmitter and CY7B933 H O TLink Receiver are pointto-point com munications building blocks that transfer data over high-speed serial

7202A

Contextual Info: M OSEL V ITEU C MS7200U7201AL/7202AL 256x9,512x9, 1Kx9 CMOS FIFO Features Descriptions • First-In/First-Out static RAM based dual port memory ■ Three densities in a x9 configuration ■ Low power versions ■ Includes empty, full, and half full status flags