TSSOP64 PACKAGE Search Results

TSSOP48

Abstract: TSSOP64 SPDT SPI STP08CL596M TSSOP24 5V SPST RELAY 74V1G66CTR 74V1G66STR 74V1T384CTR 74V1T384STR
Contextual Info: Surface mounting packages Advanced Logic ICs SOT23-8L SOT23-5L SOT323-5L Selection guide TSSOP16 TSSOP20 LFBGA96 TSSOP24 TFBGA54 SO-16 SO-20 TSSOP24 exposed-pad TSSOP48 µTFBGA42 QFN16 SO-24 TSSOP64 Flip-Chip5 SSOP24 Flip-Chip11 H (inch) W (tape width mm)

Contextual Info: Package outline TSSOP64: plastic thin shrink small outline package; 64 leads; body width 6.1 mm SOT646-1 E D A X c HE y v M A Z 64 33 A2 A 3 A1 pin 1 index A θ Lp L 1 32 w M bp e detail X 2.5 5 mm scale DIMENSIONS (mm are the original dimensions). UNIT

TSSOP64

Abstract: TSSOP-64 TSSOP64 package sot646
Contextual Info: PDF: 2003 Mar 24 Philips Semiconductors Package outline TSSOP64: plastic thin shrink small outline package; 64 leads; body width 6.1 mm SOT646-1 E D A X c HE y v M A Z 64 33 A2 A 3 A1 pin 1 index A θ Lp L 1 32 bp e detail X w M 2.5 5 mm scale DIMENSIONS (mm are the original dimensions).

TSSOP64

Contextual Info: PDF: 2000 Aug 21 Philips Semiconductors Package outline TSSOP64: plastic thin shrink small outline package; 64 leads; body width 6.1 mm SOT646-1 E D A X c HE y v M A Z 64 33 A2 A 3 A1 pin 1 index A θ Lp L 1 32 bp e 2.5 detail X w M 5 mm scale DIMENSIONS (mm are the original dimensions).

TSSOP64

Abstract: TSSOP-64 TSSOP64 package
Contextual Info: DIMENSIONS REF. mm inch MIN. TYP. MAX. MIN. A TYP. 1.1 A1 0.05 A2 0.043 0.15 0.002 0.9 0.006 64-LEAD THIN SHRINK SMALL OUTLINE 0.035 b 0.17 0.27 0.0067 0.011 c 0.09 0.20 0.0035 0.0079 D 16.9 17.1 0.665 0.673 E 8.1 E1 6.2 0.236 0.5 0.244 0.0197 K 0° 8° 0°

Contextual Info: SSTVF16859 13-bit 1 : 2 SSTL_2 registered buffer for DDR Rev. 02 — 19 July 2005 Product data sheet 1. General description The SSTVF16859 is a 13-bit to 26-bit SSTL_2 registered driver with differential clock inputs, designed to operate between 2.3 V and 2.7 V for PC1600-PC2700 applications or

A114

Abstract: JESD22 JESD78 PC3200 SSTV16859 SSTVF16859 TSSOP64
Contextual Info: SSTVF16859 13-bit 1 : 2 SSTL_2 registered buffer for DDR Rev. 02 — 19 July 2005 Product data sheet 1. General description The SSTVF16859 is a 13-bit to 26-bit SSTL_2 registered driver with differential clock inputs, designed to operate between 2.3 V and 2.7 V for PC1600-PC2700 applications or

Contextual Info: GTL1655 16-bit LVTTL-to-GTL/GTL+ bus transceiver with live insertion Rev. 01 — 11 May 2004 Product data 1. Description The GTL1655 is a 16-bit bus transceiver that incorporates HIGH-drive LOW-output-impedance 100 mA/12 Ω with LVTTL-to-GTL/GTL+ and GTL/GTL+-to-LVTTL logic level translation.

AN01026

Abstract: GTL1655 GTL1655DGG TSSOP64 2A817
Contextual Info: GTL1655 16-bit LVTTL-to-GTL/GTL+ bus transceiver with live insertion Rev. 01 — 11 May 2004 Product data 1. Description The GTL1655 is a 16-bit bus transceiver that incorporates HIGH-drive LOW-output-impedance 100 mA/12 Ω with LVTTL-to-GTL/GTL+ and GTL/GTL+-to-LVTTL logic level translation.

TSSOP64

Abstract: 74GTL1655A 74GTL1655ATTR
Contextual Info: 74GTL1655A 16 BIT LVTTL TO GTL/GTL + UNIVERSAL BUS TRANSCEIVERS WITH LIVE INSERTION • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ HIGH SPEED GTL/GTL+ UNIVERSAL TRANSCEIVER: tPD = 4.6 ns MAX. A to B at VCC = 3V COMBINES D-TYPE LATCHES AND D-TYPE FLIP-FLOPS FOR OPERATION IN

Contextual Info: CLOCK AND OSCILLATOR PRODUCT SELECTOR GUIDE SPRING 2013 SP RING 2 013 Clocks and oscillators for communications, computing and consumer applications www.silabs.com/timing Engineering for a mixed-signal world. 2 / C L O C K A N D O S C I L L AT O R S E L E C T O R

DDR2 SSTL class

Abstract: SSTL_18 DDR1-400 DDR2 SDRAM with SSTL_18 interface TVSOP-48 SSTL-18 PCK2059 SSTV16857 DDR200 hp SSTU32866
Contextual Info: Memory interfaces Support logic for memory modules and other memory subsystems Portfolio overview PC100 to PC133 • AVC, ALVC, AVCM, and ALVCH series registered drivers • PCK2509 and PCK2510 series PLL clock buffers DDR200 to DDR266 • SSTV and SSTL series registered drivers

PD-1503

Abstract: pd1503 h24 sot23-6 MS-026C PBGA272 MO-153-AB PD1002 MO-194AF NA-256 PD1704
Contextual Info: SSOP SSOP H20 H24 TSSOP L8 L20 A56 L14 L24 L16 L28 Q16 Q24 Q20 Q28 TFBGA NC64 SOIC W8 S24 PDIP W14 P20 S28 V56 A48 QSOP SOIC W16 H28 TSSOP S16 V48 BQSOP K56 B48 K48 B40 SOT23 T5 C6 T6 NA256 PBGA MSOP ZB56 PLCC J44 NA272 LFBGA NB64 NB96 NB114 U8 QFN J32 B80

TSSOP64

Abstract: 74GTL1655A 74GTL1655ATTR TSSOP64 package
Contextual Info: 74GTL1655A 16 BIT LVTTL TO GTL/GTL + UNIVERSAL BUS TRANSCEIVERS WITH LIVE INSERTION • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ HIGH SPEED GTL/GTL+ UNIVERSAL TRANSCEIVER: tPD = 4.6 ns MAX. A to B at VCC = 3V COMBINES D-TYPE LATCHES AND D-TYPE FLIP-FLOPS FOR OPERATION IN

t06 sot23

Abstract: TQFN-56 TQFN-64 ZL42 SC70-5 w08 SOT23-5 w08 TQFN56 TQFN-72 LQFP64 reel size ZG12
Contextual Info: Plastic IC Package Information Tape & Reel Tape and Reel packing system protects Pericom’s products from mechanical and electrical damage and is designed for automatic pick-and-place equipment. Pericom’s tape and reel specifications are in compliance with Electronics Industries Association standards for embossed carrier taping of sur face mount components for Automatic Handling EIA-481, current

Y8A transistor

Abstract: HD74SSTV16842
Contextual Info: HD74SSTV16842 11–bit to 22–bit Buffer with SSTL_2 Inputs and Outputs REJ03D0829-0200 Previous: ADE-205-602A Rev.2.00 Apr 07, 2006 Description The HD74SSTV16842 is a 11–bit to 22–bit buffer designed for 2.3 V to 2.7 V Vcc operation and SSTL_2 data (A)

TTP-64DV

Contextual Info: HD74SSTV16842 11–bit to 22–bit Buffer with SSTL_2 Inputs and Outputs REJ03D0829-0200 Previous: ADE-205-602A Rev.2.00 Apr 07, 2006 Description The HD74SSTV16842 is a 11–bit to 22–bit buffer designed for 2.3 V to 2.7 V Vcc operation and SSTL_2 data (A)

GTL1655

Abstract: GTL1655DGG TSSOP64 sot646
Contextual Info: INTEGRATED CIRCUITS DATA SHEET GTL1655 16-bit LVTTL-to-GTL/GTL+ bus transceiver with live insertion Product specification File under Integrated Circuits, 2001 Dec 21 Philips Semiconductors Product specification 16-bit LVTTL-to-GTL/GTL+ bus transceiver with

LK 1628

Abstract: Q02B HD74SSTV16859 HD74SSTV16859TEL Q11A
Contextual Info: HD74SSTV16859 1:2 13-bit SSTL_2 Registered Buffer REJ03D0832-0900 Previous: ADE-205-337H Rev.9.00 Apr 07, 2006 Description The HD74SSTV16859 is a 1:2 13-bit registered buffer designed for 2.3 V to 2.7 V Vcc operation and LVCMOS reset (RESET) input / SSTL_2 data (D) inputs and CLK input.

Q07A

Abstract: HD74SSTV16859 Q11A q03a
Contextual Info: To all our customers Regarding the change of names mentioned in the document, such as Hitachi Electric and Hitachi XX, to Renesas Technology Corp. The semiconductor operations of Mitsubishi Electric and Hitachi were transferred to Renesas Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog

74GTL1655

Abstract: 74GTL1655TTR TSSOP64
Contextual Info: 74GTL1655 16 BIT LVTTL TO GTL/GTL + UNIVERSAL BUS TRANSCEIVERS WITH LIVE INSERTION • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ HIGH SPEED GTL/GTL+ UNIVERSAL TRANSCEIVER : tPD = 4.6 ns MAX. A to B at VCC = 3V COMBINES D-TYPE LATCHES AND D-TYPE FLIP-FLOPS FOR OPERATION IN

Contextual Info: HD74SSTV16859 1:2 13-bit SSTL_2 Registered Buffer REJ03D0832-0900 Previous: ADE-205-337H Rev.9.00 Apr 07, 2006 Description The HD74SSTV16859 is a 1:2 13-bit registered buffer designed for 2.3 V to 2.7 V Vcc operation and LVCMOS reset (RESET) input / SSTL_2 data (D) inputs and CLK input.

Contextual Info: To our customers, Old Company Name in Catalogs and Other Documents On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the old company name remains in this document, it is a valid

74GTL1655

Abstract: 74GTL1655TTR TSSOP64 l30pf
Contextual Info: 74GTL1655 16 BIT LVTTL TO GTL/GTL + UNIVERSAL BUS TRANSCEIVERS WITH LIVE INSERTION • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ HIGH SPEED GTL/GTL+ UNIVERSAL TRANSCEIVER : tPD = 4.6 ns MAX. A to B at VCC = 3V COMBINES D-TYPE LATCHES AND D-TYPE FLIP-FLOPS FOR OPERATION IN