TS28 Search Results

TS280-A89Z

Contextual Info: TS280—A89Z December 1989 FUJITSU DATA SHEET • MB82B71-15/-20 64K BIT HIGH SPEED BI-CMOS SRAM 65,536-WORD x 1-BIT Bi-CMOS HIGH SPEED STATIC RANDOM ACCESS MEMORY The Fujitsu MB82B71 is a 65,536 words by 1 bits static random access memory fabricated with a

Contextual Info: TS281-A89Z Decem ber 1989 FUJITSU DATA SHEET MB82B81-15/-20 256K BIT HIGH SPEED BI-CMOS SRAM 262,144-WORD x 1-BIT Bi-CMOS HIGH SPEED STATIC RANDOM ACCESS MEMORY The Fujitsu MB82B81 is a 65,536 words by 1 bits static random access memory fabricated with a CMOS silicon gate process. To make power dissipation lower and high speed, peripheral

TS28C16A

Abstract: cmos prom
Contextual Info: ñ7D D S G S-THOMSON ' " g - ' * * * * T 7^2^37 DGlDSt.3 B ,- ^ I^ ^ ^ Ï^ I^ S À a iC Ë ^ O M PRO D U CT PREVIEW I CMOS 16,384-B IT 2K x 8 DESCRIPTION ELECTRICALLY The TS28C16A is a fast, low power, 5 V only CMOS EEPROM requiring a simple interface for in-system programming.

TS280-A89Z

Contextual Info: TS280-A89Z December 1989 FUJITSU DATA SHEET • M B82B71-15/-20 64K BIT HIGH SPEED BI-CMOS SRAM 65,536-WORD x 1-BIT Bi-CMOS HIGH SPEED STATIC RANDOM ACCESS MEMORY The Fujitsu MB82B71 is a 65,536 words by 1 bits static random access memory fabricated with a

Contextual Info: XRT86VX38A 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION JULY 2013 REV. 1.0.0 GENERAL DESCRIPTION The XRT86VX38A is an eight-channel 1.544 Mbit/s or 2.048 Mbit/s DS1/E1/J1 framer and Long-haul/Shorthual LIU integrated solution featuring R3 technology

RCR20

Abstract: TLHR RCR1511 RCR20 resistor CS61535A CS61574A CS61575 CS61581 CS62180A CS62180B
Contextual Info: CS62181 — Advanced Product Databook CIRRUS LOGIC FEATURES • Integrated E1 Framer for 2.048 Mbits/s Applications ■ Meets ITU-T G.704, G.706, and G.732, ETSI ETS 300-011, and ITU-T 1.431 ■ Support for CRC-4 Framing Standards and CAS/CCS Signaling Formats

DMO 565 R

Abstract: dmo 465 Twelve NC Code
Contextual Info: xr XRT86L34 PRELIMINARY QUAD T1/E1/J1 FRAMER/LIU COMBO NOVEMBER 2004 REV. P1.1.6 GENERAL DESCRIPTION The XRT86L34 is a four-channel 1.544 Mbit/s or 2.048 Mbit/s DS1/E1/J1 framer and LIU integrated solution featuring R3 technology Relayless, Reconfigurable, Redundancy .

scr FIR 3d

Abstract: A9RV data sheet scr fir 3d SCR FIR 3 D manual PACE PSR 800 Plus ta2aa f8125 F46E Nippon capacitors A-20
Contextual Info: DSP56311 User’s Manual 24-Bit Digital Signal Processor DSP56311UM/D Revision 1.0, October 1999 OnCEÉ and Mfax are trademarks of Motorola, Inc. Intel“ is a registered trademark of the Intel Corporation. All other trademarks are those of their respective owners.

5.1 home theatre assembling

Abstract: marking HBAR intel 945 crb MF823 RS-422 to spi converter DSP56300 DSP56302 HC11 national marking code TTL 74215
Contextual Info: DSP56302 OVERVIEW 1 SIGNAL/CONNECTION DESCRIPTIONS 2 MEMORY CONFIGURATION 3 CORE CONFIGURATION 4 GENERAL PURPOSE I/O 5 HOST INTERFACE HI08 6 ENHANCED SYNCHRONOUS SERIAL INTERFACE 7 SERIAL COMMUNICATION INTERFACE (SCI) 8 TIMER MODULE 9 ON-CHIP EMULATION MODULE

Contextual Info: DS2181 DS2181 CEPT PRIMARY RATE TRANSCEIVER DALLAS SEMICONDUCTOR FEATURES • Single chip primary rate transceiver meets CCITT standards G.704 and G.732 • Supports new CRC4-based framing standards and CAS and CCS signalling standards • Simple serial interface used for device

TS63

Contextual Info: Preliminary Information This document contains information on a product under development. The parametric information contains target parameters that are subject to change. CN8472/8474 Multichannel Synchronous Communications Controller MUSYCC Product Description

ST10Nm

Abstract: 32000K
Contextual Info:  STLC5465B MULTI-HDLC WITH n x 64 SWITCHING MATRIX ASSOCIATED . . . . . . . . . . . . . 32 TxHDLCs WITH BROADCASTING CAPABILITY AND/OR CSMA/CR FUNCTION WITH AUTOMATIC RESTART IN CASE OF TX FRAME ABORT 32 RxHDLCs INCLUDING ADDRESS RECOGNITION 16 COMMAND/INDICATE CHANNELS 4 OR

siemens b 58 468 la intel 80

Abstract: PEB 2261 ic 8279 rabbit 5000 ELIC - PEF 20550 PCR 406 J RDD 17-33 TSN2 SICOFI PEB 2261 N V2.0 PEF 2261 N
Contextual Info: ICs for Communications Extended Line Card Interface Controller ELIC PEB 20550 PEF 20550 Versions 1.3 User’s Manual 01.96 T2055-0V13-M1-7600 Edition 01.96 This edition was realized using the software system FrameMaker. Published by Siemens AG, Bereich Halbleiter, MarketingKommunikation, Balanstraße 73,

XS85

Abstract: XS42 cecl 080 PEB 2254-H smd marking code zcs FALC54 PCM24 PCM30 PEB2254 P-MQFP-80-1
Contextual Info: ICs for Communications Framing and Line Interface Component for PCM 30 and PCM 24 FALC54 PEB 2254 Version 1.3 Data Sheet 11.96 T2254-XV13-D1-7600 PEB 2254 Revision History: Current Version: 11.96 Previous Version: 04.96 Page Page Subjects major changes since last revision

CHN G4 136

Abstract: CHN G4 319 CHN G4 117 CHN G4 CHN 922 equivalent CHN 703 SLC96 alarm frame format chn 711 chn 037 digital clock with alarm using 8051
Contextual Info: XRT86VL3x T1/E1/J1 FRAMER/LIU COMBO - ARCHITECTURE DESCRIPTION JULY 2006 REV. 1.2.0 GENERAL DESCRIPTION The XRT86VL3x is a 1.544 Mbit/s or 2.048 Mbit/s DS1/E1/J1 framer and LIU integrated solution featuring R3 technology Relayless, Reconfigurable, Redundancy that comes in a 2-channel, 4-channel,

ana60

Abstract: AFM2 AFM8 hdlc INTEL 386EX TDA 1512 STLC5466 TQFP176 Motorola CMOS Dynamic RAM 1M x 1 1989
Contextual Info: STLC5466 64 CHANNEL-MULTI HDLC WITH N X 64KB/S SWITCHING MATRIX ASSOCIATED • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ 64 TX HDLCs with broadcasting capability and/ or CSMA/CR function with automatic restart in case of Tx frame abort

tda 11135

Abstract: motorola 68000
Contextual Info: {Z T S G S -T H O M S O N JÆ, IM » I[L I ^ [M i* STLC5464 MULTI-HDLC WITH n x 64 SWITCHING MATRIX ASSOCIATED 32 TxHDLCs WITH BROADCASTING CAPA­ BILITY AND/OR CSMA/CR FUNCTION WITH AUTOMATIC RESTART IN CASE OF TX FRAMEABORT 32 RxHDLCs INCLUDING ADDRESS REC­

sc1s 311

Abstract: CC00-CC01 DSP56300 DSP56303 HC11 national marking code mhpc 7.1 channel assembled home theater circuit diagram
Contextual Info: DSP56303UM/AD DSP 56303 User’s Manual M o t o r o l a ’ s H i g h - P e r f o r m a n c e D S P T e c h n o l o g y This document and other documents can be viewed on the World Wide Web at http://www.motorola-dsp.com. This manual is one of a set of three documents. You need the following

tundra scv64

Contextual Info: Table of Contents 1 General Information. 1-1 1.1 Introduction. 1-1 1.2

Thyristor chn 542

Abstract: transistor chn 952 CHN 952 transistor CHN 64 946 SEMP 690 tS27R BA 3166 MB91F644 chn 348 CM71-00104
Contextual Info: FUJITSU MICROELECTRONICS CONTROLLER MANUAL CM71-10154-1E FR80 32-BIT MICROCONTROLLER MB91640A/645A Series HARDWARE MANUAL FR80 32-BIT MICROCONTROLLER MB91640A/645A Series HARDWARE MANUAL For the information for microcontroller supports, see the following web site.

Contextual Info: m i c r o e l e c t r o n i c s group Preliminary Data Sheet December 1997 Lucent Technologies Bell Labs Innovations TEC03264 32-Channel Echo Canceler Features Applications Overall Device • Digital terrestrial communication networks ■ Dual-convergence voice band echo canceler

Contextual Info: Dual T1/E1/J1 Long Haul / Short Haul Transceiver IDT82P2282 Version 8 February 26, 2008 6024 Silver Creek Valley Road, San Jose, CA 95138 Telephone: 800 345-7015 • TWX: 910-338-2070 • FAX: (408) 284-2775 Printed in U.S.A. 2008 Integrated Device Technology, Inc.

motorola 6800 8bit hardware architecture

Abstract: 6800 intel microprocessor pin diagram motorola 6800 8bit software architecture AFM8 VCXO 2048khz crystal 68020-16 80C186-16 AFM2 ana61 control unit of 68020
Contextual Info:  STLC5465B MULTI-HDLC WITH n x 64 SWITCHING MATRIX ASSOCIATED . . . . . . . . . . . . . 32 TxHDLCs WITH BROADCASTING CAPABILITY AND/OR CSMA/CR FUNCTION WITH AUTOMATIC RESTART IN CASE OF TX FRAME ABORT 32 RxHDLCs INCLUDING ADDRESS RECOGNITION 16 COMMAND/INDICATE CHANNELS 4 OR

tda 11135

Abstract: TDA 11115 VCXO 2048khz crystal MICROPROCESSOR 68000 intel 80c188 intel 81 imo tdms timer tda 11135 voltage data 68020-16 80C188
Contextual Info: 7 7 S G S -T H O M S O N @ 03 iHi glT[ïM 0(g@ STLC 5464 M U LTI-H D LC W ITH n x 64 SW ITC H IN G M ATRIX ASSO CIATED A D VA N C E DATA • 32 Tx HD LC s W ITH BR O A D C A S T IN G C A P A ­ BILITY A N D /O R C S M A /C R FU N C TIO N W ITH A U T O M A T IC R ES TA R T IN C AS E O F Tx