TREY Search Results

er36 transformer

Contextual Info: S TANDARD PRO DUCT PM PMC-Sierra, inc. PM 7345 S/UNI-PDH ISSUE 5 SATURN User Network Interface forPD H PM7345 S/UNI- fTM PDH S/UNI-PDH S A T U R N U s e r N e t w o r k I n t e r f a c e for A T M P l e s i o c h r o n o u s Di gi t al H i e r a r c h y Pre lim ina ry

Contextual Info: [PIM2>[E U T P^E^OO in te i 80960HA/HD/HT 32-BIT HIGH-PERFORMANCE SUPERSCALAR PROCESSOR • Binary Compatible with Other80960 Processors • Two Instructions/Clock Sustained Execution 32-Bit Parallel Architecture — Load/Store Architecture — Sixteen 32-Bit Global Registers

TS PQ4 12

Abstract: TS PQ4 24 ts pq4 10 TS PQ4 20 TS PQ4 120
Contextual Info: in y 1.0 80960HA/HD/HT About This Document This document describes the parametric performance of Intel’s 80960Hx embedded superscalar microprocessors. Detailed descriptions for functional topics — other than parametric performance — are published in the i960 H x M icroprocessor U ser’s Guide 272484 .

transistor b1240

Abstract: B1240 transistor B1240 r DDR333 PAR64 PC2700 REQ64
Contextual Info: Intel 80333 I/O Processor Datasheet Product Features • ■ ■ ■ ■ ■ ■ Integrated Intel XScale® core — 500, 667 and 800 MHz — ARM* V5TE Compliant — 32 KByte, 32-way Set Associative Instruction Cache with cache locking — 32 KByte, 32-way Set Associative Data

VAA33

Abstract: AA36 ZSF200
Contextual Info: Switch Fabric Data Sheet 89TSF552 Preliminary Information* Description is configurable up to OC-192. Always non-blocking architecture across destination, traffic type cell, packet , and class of service (CoS). ◆ Supports up to 4 egress subports per switch port.

SMD codes

Abstract: 063310
Contextual Info: QuadPHY 10GX ASSP Telecom Standard Product Data Sheet Released PM8358 QuadPHY® 10GX 4 X 1.2 to 3.2 Gbit/s Quad, Fully Redundant, XAUI to XGMII, 10 Gigabit Ethernet / Fibre Channel Physical Layer Device Data Sheet Released Issue No. 5: April 2004 Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.

Contextual Info: Datasheet R8C/38T-A Group RENESAS MCU 1. R01DS0081EJ0100 Rev.1.00 Dec 09, 2011 Overview 1.1 Features The R8C/38T-A Group of single-chip microcontrollers MCUs incorporates the R8C CPU core, which provides sophisticated instructions for a high level of efficiency. With 1 Mbyte of address space, the CPU core is capable of

Contextual Info: Datasheet R8C/M13B Group RENESAS MCU 1. R01DS0005EJ0200 Rev.2.00 Mar 19, 2012 Overview 1.1 Features The R8C/M13B Group of single-chip microcontrollers MCUs incorporates the R8C CPU core, which provides sophisticated instructions for a high level of efficiency. With 1 Mbyte of address space, the CPU core is capable of

Non-Pipelined processor

Abstract: 80960HA 80960HD 80960HT A80960HT60 272495
Contextual Info: 80960HA/HD/HT 32-Bit High-Performance Superscalar Processor Datasheet Product Features • ■ ■ ■ ■ ■ 32-Bit Parallel Architecture — Load/Store Architecture — Sixteen 32-Bit Global Registers — Sixteen 32-Bit Local Registers — 1.28 Gbyte Internal Bandwidth

8kx1 RAM

Abstract: 82c pci isa tagram
Contextual Info: Pentium hyperCache™ Chipset System Controller Featu res Supports mixed standard page-mode and EDO DRAMs Supports the VESA Unified Memory Architecture VUMA Support fo r standard 72-bit-wide DRAM banks • Provides control fo rth e cache, system memory, and the

80960HT

Abstract: 80960HA 80960HD 272495 D1365 D2962 2xcore
Contextual Info: ADVANCE INFORMATION 80960HA/HD/HT 32-BIT HIGH-PERFORMANCE SUPERSCALAR PROCESSOR • 32-Bit Parallel Architecture ■ 3.3 V Supply Voltage — — — — Load/Store Architecture Sixteen 32-Bit Global Registers Sixteen 32-Bit Local Registers 1.2 Gbyte Internal Bandwidth

Contextual Info: 5TE T> m 0257527 D0312M0 b37 • AMD3 _ A]>V fllCRQ TELECOM -p-ir-n- ? Am7901 B/C Advanced Micro Devices Subscriber Line Audio-Processing Circuit (SLAC) WORLD-CHIP DISTINCTIVE CHARACTERISTICS ■ Combination CODEC and Fitter ■ No trimming or adjustments required

R5F21368snfp

Abstract: 06B2D 0025DH 00285H
Contextual Info: Datasheet R8C/36T-A Group RENESAS MCU 1. R01DS0055EJ0100 Rev.1.00 Dec 09, 2011 Overview 1.1 Features The R8C/36T-A Group of single-chip microcontrollers MCUs incorporates the R8C CPU core, which provides sophisticated instructions for a high level of efficiency. With 1 Mbyte of address space, the CPU core is capable of

06B2D

Abstract: 0029E 000E8H 002C1H 0028b 0027AH 0025DH 00285H 06B13
Contextual Info: Preliminary Datasheet Specifications in this document are tentative and subject to change. R8C/38T-A Group RENESAS MCU 1. R01DS0081EJ0001 Rev.0.01 Feb 23, 2011 Overview 1.1 Features The R8C/38T-A Group single-chip microcontrollers MCUs incorporate the R8C CPU core, which provides

R5F21368snfp

Abstract: R5F21368 r5f2136csnfp 0025DH 00285H
Contextual Info: Preliminary Datasheet Specifications in this document are tentative and subject to change. R8C/36T-A Group RENESAS MCU 1. R01DS0055EJ0001 Rev.0.01 Jan 28, 2011 Overview 1.1 Features The R8C/36T-A Group single-chip microcontrollers MCUs incorporate the R8C CPU core, which provides

Motor driven potentiometers

Contextual Info: Rotary Potentiometers/EUWM Malaysia Motor Driven Potentiometers Type: EUWM n Features l A space-saving-type, motor-driven potentiometer of which the manual operating shaft is aligned with the motor shaft l Dustproof structure for both reduction mechanism part and volume control part

1357-ball

Abstract: AH31 ESL rating 81348 intel G31 circuit diagram free 3150* intel intel G31 maintenance
Contextual Info: Intel 413808 and Intel®413812 SAS/SATA I/O Controllers Datasheet Product Features „ „ „ „ „ „ „ The Intel® 413808 SAS/SATA I/O Controller is a single Intel XScale® core controller The Intel® 413812 SAS/SATA I/O Controller is a two Intel XScale® core controller

system functions and objectives for 4-bit synchronization counter

Abstract: PM4341 PM7321 T1X14
Contextual Info: -an/ir1pM c's,era'inc- r I Y IV * PRELIMINARY INFORMATION PM7321PLPP PHYSICAL LAYER PROTOCOL PROCESSOR FEATURES • Implements the ATM physical layer for Broadband ISDN according to CCITT Recommendation 1.432. • Implements the Physical Layer Convergence Protocol for DS1 and DS3 based

AC+121+V+TPI+121

Contextual Info: 2: 43 AM TUPP 2488 ASSP Telecom Standard Product Data Sheet Released ay ,1 8N ov em TUPP™ 2488 be r, 20 04 03 :5 PM5364 Data Sheet Released Issue No. 7: August 2004 Do wn l oa de d by C on te n tT ea m of Pa r tm in er In co n Th ur sd SONET/SDH Tributary Unit Payload

L-SG1010-A3

Abstract: SG1010-A3 tx5n 100OHM REF10 SG1010 SG2010 StarGen pci
Contextual Info: SG1010 Data Sheet Revision Information: 5.1 StarGen, Inc., 225 Cedar Hill Street, Suite 22, Marlborough, MA 01752 www.stargen.com October 2004 StarGen, Inc. believes the information in this publication is correct; however, the information is subject to change

Contextual Info: 2: 59 AM TUPP 2488 ASSP Telecom Standard Product Data Sheet Released ay ,1 8N ov em TUPP™ 2488 be r, 20 04 03 :5 PM5364 Data Sheet Released Issue No. 7: August 2004 Do wn l oa de d by C on te n tT ea m of Pa r tm in er In co n Th ur sd SONET/SDH Tributary Unit Payload

FT-920 Switch Board Mod

Abstract: FT-101Z 70.455 FT-847 ROOFING IC-756 FT-1000MP "Crystal Filters" FT-1000D 9850 RECEIVER
Contextual Info: Summer 2008 Catalog Welcome! -60 dB to its bandwidth at -6 dB is the filter’s “shape factor.” A perfect shape factor would be 1. Typically, we encounter shape factors of 1.5 to 3.0 or more for crystal filters in current amateur use. Refer to page 14 for

Contextual Info: Datasheet R8C/36T-A Group RENESAS MCU 1. R01DS0055EJ0100 Rev.1.00 Dec 09, 2011 Overview 1.1 Features The R8C/36T-A Group of single-chip microcontrollers MCUs incorporates the R8C CPU core, which provides sophisticated instructions for a high level of efficiency. With 1 Mbyte of address space, the CPU core is capable of

RTM 866 - 485

Abstract: PM5326 PMC-2021113 diode 1Y4 bit-slice MPSA reference TILE3 em 262 "Frame rate conversion"
Contextual Info: 4: 40 AM TSE Nx160 ASSP Telecom Standard Product Data Sheet Released ay ,2 2D ec em TSE Nx160 be r, 20 04 12 :3 PM5376 Data Sheet Proprietary and Confidential Released Issue No. 7: July 2004 Do wn l oa de d by C on te n tT ea m of Pa rtm in er In co n W ed