TRAP SPARC Search Results

nxor

Abstract: TSC695 20 pin edac
Contextual Info: Trap Generation Under EDAC and Parity Protection This application note describes the trap mechanisms used by the TSC695 processor when accessing memory areas that are protected by EDAC and parity. The main principles of the trap generation when data protection is enabled on TSC695 are

sparclite

Abstract: MB86930
Contextual Info: SPARClite MANIPULATING REGISTER WINDOWS IN WINDOW OVERFLOW AND UNDERFLOW CONDITIONS FOR TRAP HANDLERS ƒ APPLICATION NOTE 2 FUJITSU MICROELECTRONICS, INC. SPARClite is a trademark of SPARC International, Inc., licensed exclusively to Fujitsu Microelectronics, Inc.

AT697

Abstract: 4409A ASR16 AT697E atmel edac AT697E-2E-E sdram edac
Contextual Info: Active Errata List • • • • • • • • Multiplier/Divider Failure on Negative Operands Treatments Call Return Address Failure with Large Displacement Byte and Half-word Write to SRAM Failure when Executing from SDRAM Wrong PC stored during FPU exception trap

vhdl code for 16 BIT BINARY DIVIDER

Abstract: ASR16 4 bit binary multiplier Vhdl code SDRAM edac atmel edac AT697E vhdl code for 4 bit ram vhdl sdram
Contextual Info: Active Errata List 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. Multiplier/Divider Failure on Negative Operands Treatments Call Return Address Failure with Large Displacement Byte and Half-word Write to SRAM Failure when Executing from SDRAM Wrong PC stored during FPU exception trap

0x00000001

Abstract: edac TSC695
Contextual Info: EDAC Testing Injection of Correctable and Uncorrectable Errors This application note describes how to test the TSC695 trap mechanism when the EDAC is enabled. A simple EDAC test procedure is described in this application note. To illustrate the procedure, two test cases consisting in single error injection and multiple errors injection are provided.

mb8693

Abstract: mb8683 10H14 MB86830 0x00000850
Contextual Info: MB86860 Series Programming Manual SPARClite MB86860 Series Programming Manual Edition 1.0 - Jun. 22, 1999 Fujitsu Ltd. MB86860 Series Programming Manual Contents 0. Introduction . 0-1

Contextual Info: C hapter E10 Floating-Point Unit E10.1 Overview of the MB86936 Floating-Point Unit The MB86936 FPU fully conforms to the ANSI/IEEE Standard 754-1985, the SPARC Architecture Version 8 specification, and the SPARC IEEE754 Implementation Recommendation except for the Nonstandard FP NS=1 mode implementation.

W8701

Abstract: instruction set Sun SPARC T3 Cy7C601 weitek 8701 W8701-40 weitek instruction set Sun SPARC T5 w8720 a2054
Contextual Info: W8701 INTEGRATED SPARC-COMPATIBLE PROCESSOR FAMILY M arch 1992 Chapter 1. Technical Overview 1.1. Features SINGLE-CHIP SPARC-COMPATIBLE IU/FPU HIGH PERFORMANCE Combines SPARC-compatible integer and floating-point units on a single chip Highest-performance SPARC-compatible processor on

Contextual Info: C h a pt er E10 Floating-Point Unit E10.1 Overview of the MB86936 Floating-Point Unit The MB86936 FPU fully conforms to the A N SI/IEEE Standard 754-1985, the SPARC Architecture Version 8 specification, and he SPARC IEEE754 Implementation Recommendation except for the Nonstandard FP (NS=1 mode implementation.

Contextual Info: C h a pter 7 S £ 3 & § 5 S 5 3 £ S £ 8 S £ i8 3 S $ 3 liS 8 £ Instruction Set This chapter presents the SPARClite processor instruction set. Sections discussing recommended assembly language syntax, a table of instructions listed by opcode, and an alphabetized instruction set reference are included.

sparclite

Abstract: MB86930 CB123 XCB100 tl 741 X0010 ASR17 EWS300-24 instruction manual
Contextual Info: SECTION 1 MB86930 Chapter 7: Instruction Set Chapter 8: JTAG MB86930 - SPARClite User’s Manual SPARClite User’s Manual Chapter 7: Instruction Set 7.1 Suggested Assembly Language Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1

mb86901

Contextual Info: F U J IT S U High Performance 32-Bit RISC Processor SPARC FEATURES • Architecture supports scalability towards faster technologies • Address presentation which supports highperformance cache • 15 times V A X ™ 11/780 equivalent MIPS typical performance

al131

Abstract: instruction set Sun SPARC T6 coreware library LCB007 Enhanced Self-Embedding Processor Core
Contextual Info: m LSI 53D4f l D4 DDl Ql Mt fl?2 CW803 and CW807 SPARC Embedded Processors User’s Manual A Core Ware Product MV72-000106-99 A 5304A04 0010147 70T « L L C This document is preliminary. As such, it contains data derived from func­ tional simulations and performance estimates. LSI Logic has not verified either

N13H1

Abstract: tms390 A23 1101-01 TMS390C602 TMS390C601 TMS390C602A TMS390C
Contextual Info: ú£C M 1 TMS390C602A SPARC’" FLOATING-POINT UNIT I»« _ SPKS006 — D3669. JANUARY 1991 — Internal Data Coherency Logic Checks for Data Dependencies — Notifies IU if a Floating-Point Exception Has Occurred Single-Chip, SPARC^-Compatlble

MB86903

Abstract: instruction set Sun SPARC T3 CY7C601
Contextual Info: MB86903 ~ FUJITSU SPARC -BASED IU/FPU AUGUST 1991 DATA SHEET FE A T U R E S _ G E N E R A L D E S C R IP T IO N • Single chip im plementation o f SPARC IU and FPU based upon the SPARC architecture The MB86903 is the first commercially available pro­

MB86930

Abstract: bcd to 7 segment converter ASR16 xnor fairchild semiconductor ic Record STA 12
Contextual Info: SPARClite User’s Manual May ’94 Fujitsu Microelectronics, Inc. Semiconductor Division SPARClite User’s Manual CREDITS Book design & illustration by Advanced Information Management A.I.M. , a subsidiary of Fujitsu America, Incorporated. This book, excluding the cover, was illustrated, and produced on a Sun SPARC IPC workstation using

TAG 8816

Abstract: SPARC64 Fujitsu SparC64 instruction set b32s FN 1016 0C16 1D16 3C16 IEEE754 MDTL
Contextual Info: SPARC64 VI Extensions Fujitsu Limited Release 1.3, 27 Mar. 2007 Fujitsu Limited 4-1-1 Kamikodanaka Nakahara-ku, Kawasaki, 211-8588 Japan Copyright 2006 Fujitsu Limited, 4-1-1 Kamikodanaka, Nakahara-ku, Kawasaki, 211-8588, Japan. All rights reserved. This product and related documentation are protected by copyright and

instruction set Sun SPARC T3

Abstract: C602A TMS390C601 TMS390C60 tms390 TMS390C602A C601 fpu coprocessor
Contextual Info: DÊC O9 um I TMS390C602A SPARC FLOATING-POINT UNIT _SPKS006—_D3669. JANUARY 1991 * Slngle-Chlp, SPARC'"-Compatible Floating-Point Unit FPU for the ’C601 Integer Unit (IU) • High-Performance — 25-ns Cycle Time — 4.2 Million Double-Precision Unpack

MB86831

Abstract: Fujitsu SPARC rsn 309 w 44 8683x MB8683x
Contextual Info: MB8683x User’s Guide Fujitsu Microelectronics, Inc. NICE is a trademark of Fujitsu Microelectronics, Inc. SPARC is a registered trademark of SPARC International, Inc. based on technology developed by Sun Microsystems, Inc. SPARClite is a trademark of SPARC International exclusively licensed to Fujitsu Microelectronics, Inc.

0x61

Abstract: TSC695 TSC695E
Contextual Info: TSC695E Rad-Hard Rad-Hard 32-bit SPARC SPARC 32-bit Embedded Processor Processor Embedded Errata Sheet Rev. A - December 2000 1 TSC695E Errata Sheet Information Foreword The information contained herein is subject to change without notice. No responsibility is assumed by Atmel Nantes

Spin fv-1

Abstract: FV-1 SPIN SPARC64 TAG 8816 transistor fn 1016 0C16 1D16 3C16 IEEE754 Fujitsu SparC64 instruction set
Contextual Info: SPARC64 VII Extensions Fujitsu Limited Ver 1.0, 1 Jul. 2008 Fujitsu Limited 4-1-1 Kamikodanaka Nakahara-ku, Kawasaki, 211-8588 Japan Copyright 2007, 2008 Fujitsu Limited, 4-1-1 Kamikodanaka, Nakahara-ku, Kawasaki, 211-8588, Japan. All rights reserved.

SPARC V7.0

Abstract: CY7C601 sparc v7 ERC32 CB123
Contextual Info: SPARC V7.0 Instruction Set for Embedded Real time 32–bit Computer ERC32 for SPACE Applications SPARC V7.0 Instruction Set 1. Assembly Language Syntax The notations given in this section are taken from Sun’s SPARC Assembler and are used to describe the suggested

bit310

Abstract: MB86831 MB86832 MB86833 MB86834 XX10 0b00011 burst MB86930 332 TLE 3101 Fujitsu SPARC
Contextual Info: FUJITSU SEMICONDUCTOR PM52-00004-1E PROCESSOR MANUAL SPARClite MB86830 HARDWARE MANUAL SPARClite MB86830 HARDWARE MANUAL FUJITSU LIMITED PREFACE • Purpose and intended audience The SPARClite family of 32-bit microcomputers conforms to the SPARC architecture that has

sparc v7

Abstract: simm13 SPARC V7.0 SPARC 7 diode 29 RS1 STC 8133 CB123 TSC695 FBUL
Contextual Info: Assembly Language Syntax The notations given in this section are taken from Sun’s SPARC Assembler and are used to describe the suggested assembly language syntax for the instruction definitions explained on page 5. Understanding the use of type fonts is crucial to understanding the assembly language syntax in the instruction definitions. Items in typewriterfont are literals, to be