MB8693 Search Results

0x000001D8

Abstract: sparclite fujitsu dot matrix printer circuit diagram monitor e74 0x00000128 MB86930 IS 208 MXM pin assignment E5214 e328
Contextual Info: SPARClite 930 Series Embedded Processor User’s Manual MB86936 Addendum JULY 1996, Edition 1.3 FUJITSUMICROELECTRONICS, INC. SPARClite User’s Manual – MB86936 Addendum Overview of the MB86936 1 Caches 2 Bus Interface Unit 3 DRAM Controller 4 DMA Controller

sparclite

Abstract: MB86930 SPARC 7 ASR16 ASR17 0x0000FF0C ASR311
Contextual Info: SECTION 1 MB86930 Chapter 1: Overview Chapter 2: Programmer’s Model MB86930 - SPARClite User’s Manual CONTENTS SECTION 1 Chapter 1: Section 1: MB86930 Chapter 1: Overview 1.1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1

Contextual Info: C h a pt er E10 Floating-Point Unit E10.1 Overview of the MB86936 Floating-Point Unit The MB86936 FPU fully conforms to the A N SI/IEEE Standard 754-1985, the SPARC Architecture Version 8 specification, and he SPARC IEEE754 Implementation Recommendation except for the Nonstandard FP (NS=1 mode implementation.

Contextual Info: MB86935 Bus Interface Unit H3.1 Overview of Bus Interface Unit The BIU on the MB86935 includes all the features of the MB86930, and in addition offers the following: • Option to run core at double the frequency of the Bus Interface Unit, • Four-word burst mode for instruction fetches and data loads,

MARKING cfk

Abstract: marking code CFK MB86936A
Contextual Info: MB86936 FUJITSU 930 SERIES 32-BIT RISC EMBEDDED PROCESSOR AUGUST, 1996 • • • • JTAG test interface Emulator support hardware Single vector trapping Power down modes, with global or selective power down • 0.5 micron gate, 3 level metal CMOS technology,

B86931

Abstract: MB86931
Contextual Info: C h a pter A4 M B86931 Serial Data Transmitters And Receivers The MB86931 features two independent serial communication units designated SDTRO and SDTR1. The SDTRs support synchronous and asynchronous data transfer modes, and are program-compatible with existing industry-standard

Contextual Info: MB86932 FUJITSU SPARCIite 32-BIT RISC EMBEDDED PROCESSOR MAY 25, 1994 FEATURES • 4 0 M H z 2 5 n s/cy cle operating frequency • SPARC high perform ance R IS C architecture • 8 K by tes 2 -way set associative instruction cach e • 2 K bytes 2 - way set associative data cache

MB86986

Abstract: IEEE754 MB86930 0x00001000
Contextual Info: SPARClite MB86930 TO MB86936 MIGRATION APPLICATION NOTE 5 FUJITSU MICROELECTRONICS, INC. REVISION 01 APPLICATION NOTE 5 INTRODUCTION ification, and the SPARC IEEE754 Implementation Recommendation with the Nonstandard FP NS=1 mode enabling “flush to zero” treatment of denormalized operands or results as permitted by the recommendation.

t20s

Abstract: SQFP208 MB86930 MB86936A
Contextual Info: MB86936 930 SERIES 32–BIT RISC EMBEDDED PROCESSOR AUGUST, 1996 • JTAG test interface FEATURES • Emulator support hardware • 50 MHz version with clock doubling • SPARC high performance RISC architecture • High Performance SPARC FPU, ANSI/IEEE 754

MB86933

Abstract: MB86933-20
Contextual Info: MB86933 FUJITSU SPARCIite 32-BIT RISC EMBEDDED PROCESSOR MAY 2 5 , 1994 FEATURES_ _ • 20 MHz 50ns/cycle operating frequency • SPARC high performance RISC architecture • 6 window, 104 word register file • Fast interrupt response time

MB86901

Abstract: MB89251 Fujitsu MB86900 mb86900 MB86902 instruction set Sun SPARC T8 MB86931-20ZF-G
Contextual Info: MB86931 930 Series 32–BIT RISC EMBEDDED PROCESSOR/ INTERRUPT CONTROLLER/TIMER/USART MAY 24, 1994 FEATURES • 40 MHz 25ns/cycle operating frequency • SPARC high performance RISC processor – 2 Kbytes 2–way set associative instruction and data caches.

SPARC v8 architecture BLOCK DIAGRAM

Abstract: G545 MB86930 G514 0101 g547
Contextual Info: SPARClite 930 Series Embedded Processor User’s Manual MB86933H Addendum JULY 1996, EDITION 1.0 FUJITSU MICROELECTRONICS, INC. Overview of the MB86933H 1 Programmer’s Model 2 Internal Architecture 3 MB86933H Interrupt Request Controller 4 External Interface

80241

Abstract: SPARClite
Contextual Info: MB86933H DEVELOPMENT KIT September 1995 INTRODUCTION Fujitsu introduces a full-featured development kit for the SPARClite RISC processor. The kit includes necessary hardware and software to allow a user to evaluate SPARClite’s performance. This can be done by the

Contextual Info: M B86934 FUJITSU MB8693X 32-BIT RISC EMBEDDED PROCESSOR September 2 1 ,1 9 9 4 PRELIMINARY INFORMATION FEATURES_ _ • 60 MHz operating frequency • SPARC» high performance RISC architecture • High Performance SPARC FPU, ANSI/IEEE 754

MB86930

Abstract: rf 433 mir psr 53-9 sparclite IEEE754 MB86960 4 bit modified booth multipliers
Contextual Info: SECTION 1 MB86930 Chapter 3: Internal Architecture Chapter 4: External Interface Chapter 5: Programming Considerations Chapter 6: System Design Considerations MB86930 - SPARClite User’s Manual Chapter 3: Internal Architecture 3.1 Integer Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2

MB86930

Abstract: 179-PIN
Contextual Info: 355K Data Sheet User's Manual 118K Application Note MB86930 PROCESSOR RISC processing optimized for embedded applications The MB86930 architecture offers 32-bit RISC performance optimized for embedded applications. The integer unit executes nearly every instruction in one

g545

Contextual Info: R iB b I i i i i i i i i i i i i i i External Interface The processor external interface consists of signals for bus operations and for system control. This chapter details the MB86933H signal set, describes basic bus timing, and describes the programmable wait-state generator, on-chip timer, and same-page

Contextual Info: MB86933 FUJITSU PRELIMINARY SPARClite 32-BIT RISC EMBEDDED PROCESSOR ADVANCE INFORMATION AUGUST 1992 FEATURES G EN ER A L D E S C R IP T IO N • 20 MHz 50ns/cycle operating frequency The MB86933 is the next of the SPARClite series of RISC processors which offers high performance and

AMD27C010-205DC

Abstract: RXDT-2-20-MHZ MB814260 rxdt-2 BMODE16 74F74 AM27C010-205DC MB814260-70 0x10000040 0x00000130
Contextual Info: SPARClite MB86933H BASIC CONFIGURATION SYSTEM APPLICATION NOTE 3 FUJITSU MICROELECTRONICS, INC. REVISION 01 Application Note 3 INTRODUCTION coupled companion chip, which provides general I/O functions including: This application outlines the design of a basic system using

MB86930

Abstract: QFP-208 fujitsu MB86932-20ZF-G MB86932-40ZF-G MB86932
Contextual Info: MB86932 930 Series 32–BIT RISC EMBEDDED PROCESSOR MAY 25, 1994 FEATURES • • • • • • • • • • • • • • • • • • • • • • • 40 MHz 25ns/cycle operating frequency SPARCR high performance RISC architecture 8 Kbytes 2-way set associative instruction cache

sparclite

Abstract: MB86930 CB123 XCB100 tl 741 X0010 ASR17 EWS300-24 instruction manual
Contextual Info: SECTION 1 MB86930 Chapter 7: Instruction Set Chapter 8: JTAG MB86930 - SPARClite User’s Manual SPARClite User’s Manual Chapter 7: Instruction Set 7.1 Suggested Assembly Language Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1

SPARC

Abstract: MB86936
Contextual Info: MB86936 EVALUATION KIT September 1996 DESCRIPTION SYSTEM REQUIREMENTS Fujitsu introduces a full-featured evaluation kit for the SPARClite RISC processor. The kit includes board module and software to allow a user to evaluate SPARClite’s performance. • PC/AT Compatible System 486 or better

MB86901

Abstract: mb86900 Fujitsu MB86900 MB86902 mb86930-40 MB86930-20PFV-G MB86930-40CR-G ASI1 MARKING MB86930 MB86930-30ZF-G
Contextual Info: MB86930 930 Series 32-BIT RISC EMBEDDED PROCESSOR May 25, 1994 Included to maximize the performance of the system with minimum glue logic, are chip select outputs, programmable wait-state generation and built-in support for a high performance connection to page-mode DRAM. See

MB86933H

Abstract: MB86930 MB86931 instruction set Sun SPARC T8 ADR27
Contextual Info: MB86933H 930 Series 32–BIT RISC EMBEDDED PROCESSOR November 1996 ADVANCE INFORMATION FEATURES • 25 MHz 40ns/cycle operating frequency • SPARC V8 high–performance RISC architecture • 1 KByte, direct mapped instruction cache • Flexible locking mechanism for instruction cache