TRANSMISSION LINE EYE PATTERN Search Results

S-PQFP-G80 Board Layout

Abstract: circuit diagram for sma AS BOX M
Contextual Info: TMDS341 www.ti.com SLLS660 – AUGUST 2005 3-TO-1 DVI/HDMI SWITCH FEATURES • • • • • • • • • Designed for Signaling Rates up to 1.65 Gbps in Support of UXGA Display Differential Interface Compatible with Transition Minimized Differential Signaling

Contextual Info: DS42MB200 DS42MB200 Dual 4.25 Gbps 2:1/1:2 CML Mux/Buffer with Transmit Pre-Emphasis and Receive Equalization Texa s In s t r u m e n t s Literature Number: SNOSAT8F DS42MB200 Sem iconductor Dual 4.25 Gbps 2:1/1:2 CML Mux/Buffer with Transm it PreEmphasis and Receive Equalization

Contextual Info: SN65MLVD080 SN65MLVD082 www.ti.com SLLS581B − SEPTEMBER 2003 − REVISED SEPTEMBER 2005 8ĆCHANNEL HALFĆDUPLEX MĆLVDS LINE TRANSCEIVERS FEATURES D Low-Voltage Differential 30-Ω to 55-Ω Line Drivers and Receivers for Signaling Rates 1 Up to 250 Mbps; Clock Frequencies Up to 125

Contextual Info: SN65LVDS33, SN65LVDT33, SN65LVDS34, SN65LVDT34 HIGHĆSPEED DIFFERENTIAL RECEIVERS SLLS490B − MARCH 2001 − REVISED NOVEMBER 2004 D 400-Mbps Signaling Rate1 and 200-Mxfr/s D D D D D D D D D D D Data Transfer Rate Operates With a Single 3.3-V Supply −4-V to 5-V Common-Mode Input Voltage

Contextual Info: SN65MLVD080 SN65MLVD082 www.ti.com SLLS581B − SEPTEMBER 2003 − REVISED SEPTEMBER 2005 8ĆCHANNEL HALFĆDUPLEX MĆLVDS LINE TRANSCEIVERS FEATURES D Low-Voltage Differential 30-Ω to 55-Ω Line Drivers and Receivers for Signaling Rates 1 Up to 250 Mbps; Clock Frequencies Up to 125

Contextual Info: TLK2208 8ĆPORT GIGABIT ETHERNET TRANSCEIVER SLLS556B − DECEMBER 2002 − REVISED NOVEMBER 2003 D Eight 1.0- to 1.3-Gigabits Per Second D D D D D D D D D D Gbps Synchronizable Transceivers Low Power Consumption <1.3 W at 1.25 Gbps IEEE 802.3z Gigabit Ethernet Compliant

SN65LVDT32A

Abstract: SN65LVDS3486A SN65LVDS32A
Contextual Info: SN65LVDS32A, SN65LVDT32A, SN65LVDS3486A SN65LVDT3486A, SN65LVDS9637A, SN65LVDT9637A HIGH-SPEED DIFFERENTIAL RECEIVERS SLLS368E – JULY 1999 – REVISED JUNE 2001 D Meets or Exceeds the Requirements of D D D D D D D D D D ANSI EIA/TIA-644 Standard for Signaling

SN65LVDS100DRG4

Contextual Info: SN65LVDS100, SN65LVDT100 SN65LVDS101, SN65LVDT101 www.ti.com SLLS516C – AUGUST 2002 – REVISED JUNE 2004 DIFFERENTIAL TRANSLATOR/REPEATER FEATURES • • • • • • • • • DESCRIPTION Designed for Signaling Rates ≥ 2 Gbps Total Jitter < 65 ps

TLK1201IRCP

Contextual Info: TLK1201RCP, TLK1201IRCP ETHERNET TRANSCEIVERS SLLS506D − AUGUST 2001 − REVISED AUGUST 2004 at 1.25 Gbps D LVPECL Compatible Differential I/O on High D D D D D D D D Advanced 0.25-µm CMOS Technology No External Filter Capacitors Required Comprehensive Suite of Built-In Testability

Contextual Info: SLK2511 OC-48/24/12/3 SONET/SDH MULTIRATE TRANSCEIVER SLLS522A – JUNE 2002 – REVISED OCTOBER 2002 D Fully Integrated SONET/SDH Transceiver to D D D D D D D D Support Clock/Data Recovery and Multiplexer/Demultiplexer Functions Supports OC-48, OC-24, OC-12, Gigabit

Contextual Info: J t/i Te x a s DS80PCI402 ▼ In s t r u m e n t s 2.5 Gbps / 5.0 Gbps / 8.0 Gbps 4 Lane PCI Express Repeater with Equalization and De-Emphasis General Description The DS80PCI402 is a low power, 4 lane repeater with 4-stage input equalization, and output de-emphasis driver to enhance