TQFP-144 FOOTPRINT Search Results

Contextual Info: XC95144XV High-Performance CPLD DS051 v2.6 June 18, 2003 1 Features • • • • • • • • 144 macrocells with 3,200 usable gates Available in small footprint packages - 100-pin TQFP (81 user I/O pins) - 144-pin TQFP (117 user I/O pins) - 144-pin CSP (117 user I/O pins)

k3402

Abstract: 131C-6 XC95144XV-7TQ144I CS144 TQ100 TQ144 XAPP361 XC9500XV XC95144XV
Contextual Info: XC95144XV High-Performance CPLD DS051 v2.7 August 21, 2003 1 Features • • • • • • • • 144 macrocells with 3,200 usable gates Available in small footprint packages - 100-pin TQFP (81 user I/O pins) - 144-pin TQFP (117 user I/O pins) - 144-pin CSP (117 user I/O pins)

a6252

Abstract: CS144 TQ100 TQ144 XC9500XV XC95144XV
Contextual Info: XC95144XV High-Performance CPLD R DS051 v2.2 August 27, 2001 1 Advance Product Specification Features Power Estimation • 144 macrocells with 3,200 usable gates • Available in small footprint packages - 100-pin TQFP (81 user I/O pins) - 144-pin TQFP (117 user I/O pins)

T9423

Abstract: TQ144 XC9500XL XC95288 XC95288XL W-7510 w7510 k1739
Contextual Info: XC95288XL High Performance CPLD DS055 v1.4 March 19, 2001 5 Features • • • • • • • • • • • 6 ns pin-to-pin logic delays System frequency up to 208 MHz 288 macrocells with 6,400 usable gates Available in small footprint packages - 144-pin TQFP (117 user I/O pins)

XC95288XL-10PQG208I

Abstract: XC95288XL-10TQ144I XC95288XL-10PQG208C XC95288XL XC95288XL-10TQG144C XAPP114 XAPP427 XC9500XL XC95288 xc95288xl-7fg256c
Contextual Info: XC95288XL High Performance CPLD DS055 v1.8 July 15, 2004 5 Features • • • • • • • • • • • 6 ns pin-to-pin logic delays System frequency up to 208 MHz 288 macrocells with 6,400 usable gates Available in small footprint packages - 144-pin TQFP (117 user I/O pins)

Contextual Info: XC95288XL High Performance CPLD DS055 v1.6 May 27, 2003 5 Features • • • • • • • • • • • 6 ns pin-to-pin logic delays System frequency up to 208 MHz 288 macrocells with 6,400 usable gates Available in small footprint packages - 144-pin TQFP (117 user I/O pins)

XC95288XL pinout

Abstract: XC95288XL XC95288XL-7PQ208I XC95288XL-7TQ144I XC95288XL-10PQ208I XC95288XL-10TQ144I marking G18 XC95288XL-10-PQ208 XC95288XL-6FG256C XAPP114
Contextual Info: XC95288XL High Performance CPLD DS055 v1.7 August 21, 2003 5 Features • • • • • • • • • • • 6 ns pin-to-pin logic delays System frequency up to 208 MHz 288 macrocells with 6,400 usable gates Available in small footprint packages - 144-pin TQFP (117 user I/O pins)

XC95288XL10TQG144I pinout

Abstract: XC95288XL PQG208 XC95288XL pinout XC95288XL-10TQG144C fgg256 XC95288XL XC95288XL-7CS280C XC95288XL-10FGG256I XC95288XL-7TQ144I pqg208
Contextual Info: XC95288XL High Performance CPLD R DS055 v2.1 April 3, 2007 5 Features • • • • • • • • • • • 6 ns pin-to-pin logic delays System frequency up to 208 MHz 288 macrocells with 6,400 usable gates Available in small footprint packages - 144-pin TQFP (117 user I/O pins

XC95144XL-10TQG100C

Abstract: XC95144XL-10TQ100I XC95144XL-10CSG144C XC95144XL-10TQ144I XC95144XL-5-TQ100 XC95144XL-10TQG144C xc95144xl XC95144XL-10TQG100I XC95144XL-7TQ100C TQFP 100 PACKAGE footprint
Contextual Info: XC95144XL High Performance CPLD R DS056 v2.0 April 3, 2007 Features • • • • • • • • • • • 5 ns pin-to-pin logic delays System frequency up to 178 MHz 144 macrocells with 3,200 usable gates Available in small footprint packages - 100-pin TQFP (81 user I/O pins)

TQ144

Abstract: XAPP361 XC9500XV XC95288XV XC95288XV-10 XC95288XV-7
Contextual Info: u XC95288XV High-Performance CPLD R DS050 v2.5 August 21, 2003 5 Features • • • • • • • • 288 macrocells with 6,400 usable gates Available in small footprint packages - 144-pin TQFP (117 user I/O pins) - 208-pin PQFP (168 user I/O pins) - 280-pin CSP (192 user I/O pins)

atmel 216

Abstract: TQFP 132 PACKAGE TQFP216 BGA-121
Contextual Info: Packaging Introduction Atmel pairs its high-performance silicon with packages, custom designed for the company’s gate arrays. Atmel offers our gate arrays in ceramic and plastic packages. Atmel’s plastic through hole and surface mount packages come in a

Contextual Info: MachXO2 Family Data Sheet DS1035 Version 02.2, September 2013 MachXO2 Family Data Sheet Introduction January 2013 Features Data Sheet DS1035  Flexible On-Chip Clocking • Eight primary clocks • Up to two edge clocks for high-speed I/O  interfaces top and bottom sides only

LCMXO2-256 pinout

Abstract: LCMXO2-2000 pinout
Contextual Info: MachXO2 Family Data Sheet DS1035 Version 02.1, June 2013 MachXO2 Family Data Sheet Introduction January 2013 Features Data Sheet DS1035  Flexible On-Chip Clocking • Eight primary clocks • Up to two edge clocks for high-speed I/O  interfaces top and bottom sides only

MACHXO2 7000 pinout

Abstract: MachXO2-4000
Contextual Info: MachXO2 Family Data Sheet DS1035 Version 02.3, December 2013 MachXO2 Family Data Sheet Introduction January 2013 Features Data Sheet DS1035  Flexible On-Chip Clocking • Eight primary clocks • Up to two edge clocks for high-speed I/O  interfaces top and bottom sides only

Contextual Info: MachXO2 Family Data Sheet DS1035 Version 2.5, May 2014 MachXO2 Family Data Sheet Introduction February 2014 Features Data Sheet DS1035  Flexible On-Chip Clocking • Eight primary clocks • Up to two edge clocks for high-speed I/O  interfaces top and bottom sides only

Contextual Info: MachXO2 Family Data Sheet DS1035 Version 02.0, January 2013 MachXO2 Family Data Sheet Introduction January 2013 Features Data Sheet DS1035  Flexible On-Chip Clocking • Eight primary clocks • Up to two edge clocks for high-speed I/O  interfaces top and bottom sides only

Contextual Info: MachXO2 Family Data Sheet DS1035 Version 02.4, February 2014 MachXO2 Family Data Sheet Introduction February 2014 Features Data Sheet DS1035  Flexible On-Chip Clocking • Eight primary clocks • Up to two edge clocks for high-speed I/O  interfaces top and bottom sides only

LCMXO2-256 pinout

Contextual Info: MachXO2 Family Data Sheet Preliminary DS1035 Version 01.2, April 2011 MachXO2 Family Data Sheet Introduction April 2011 Features Preliminary Data Sheet DS1035  Flexible On-Chip Clocking • Eight primary clocks • Up to two edge clocks for high-speed I/O 

XCR3128XL-10VQG100C

Abstract: XCR3128XL-10CS144I XCR3128XL-10TQG144I XCR3128XL-7VQG100C vqfp package pinout XCR3128XL-10CSG144C XCR3128XL-10VQG100I XCR3128XL-10VQ100I XCR3128XL-7TQG144C XCR3128XL-10VQ100C
Contextual Info: XCR3128XL 128 Macrocell CPLD R DS016 v2.6 March 31, 2006 14 Product Specification Features Description • Low power 3.3V 128 macrocell CPLD • 5.5 ns pin-to-pin logic delays The CoolRunner XPLA3 XCR3128XL device is a 3.3V 128 macrocell CPLD targeted at power sensitive designs

Contextual Info: LSI CSP • CSP Chip Size Package •CSP The FBGA (commonly known as CSP) has an area array terminal structure with solder balls on the bottom, to give it a near chip-size footprint. This high-density, compact and low-profile package technology will greatly help in the design of compact mobile equipment, such as mobile phones and

c4460

Abstract: trans C3150 BC518 TI486DX4-100 LC51-50 C5380 TM2SP64GPU TMS320C2X TMS320C204 seagate
Contextual Info: EXTENDING YOUR REACHTM NORTH AMERICAN EDITION INTEGRATION AN UPDATE ON TEXAS INSTRUMENTS SEMICONDUCTORS VOL. 13 ▼ NO. 2 ▼ MARCH 1996 ThunderSWITCH meets bandwidth demands Spurred by rapid growth in the use of networked applications such as the Internet, groupware, client/server and

lcmxo2-1200

Abstract: LCMXO2-2000 LCMXO2-256 LCMXO2-4000 LCMXO2-640 LCMXO2-256HC-4TG100I LCMXO2-7000 MACHXO2 7000 pinout file MachXO2-1200 LCMXO2-2000HC-4BG256C
Contextual Info: MachXO2 Family Data Sheet Advance DS1035 Version 01.0, November 2010 MachXO2 Family Data Sheet Introduction November 2010 Features Advance Data Sheet DS1035  Flexible On-Chip Clocking • Eight primary clocks • Up to two edge clocks per edge for high-speed 

footprint tqfp 208

Abstract: GPIO20 rtc 205 82371AB FDC37N958FR FDC37N972 QS3384
Contextual Info: APPLICATION NOTE 8.1 DUAL FOOTPRINT CONFIGURATION FOR THE FDC37N958FR AND THE FDC37N972 OVERVIEW • • • The SMSC FDC37N972 and the FDC37N958FR are 208-pin ISA Ultra I/O Controllers for mobile applications. These devices are pin-compatible with the following exceptions, which

footprint tqfp 208

Abstract: rtc 205 82371AB FDC37N958FR FDC37N972 QS3384
Contextual Info: APPLICATION NOTE 8.1 DUAL FOOTPRINT CONFIGURATION FOR THE FDC37N958FR AND THE FDC37N972 OVERVIEW • • • The SMSC FDC37N972 and the FDC37N958FR are 208-pin ISA Ultra I/O Controllers for mobile applications. These devices are pin-compatible with the following exceptions, which