TPLS Search Results

6 digit TN 70 pin LCD panel

Contextual Info: UNCONTROLLED DOCUMENT PART NUMBER REV. L C D - S 4 0 1 M1 6TF 16.50 [0.650] 1.91 [0.075] 1.50 [0.059] 12 u c tPLS. l o ,; 0.50 [0,020] 2,80 [0,110] MAX. 12,70 [0,500] j- 0.50 [0.020] 0.35 [0.014] m r OJ o CO i m u m O 0-0 o U.U:U.U 4,00 [0,157] MAX. CD sD

Contextual Info: Tecate Group ELECTRIC DOUBLE LAYER SNAP-IN CAPACITOR TYPE TPLS FEATURES • Small size and low-resistance • Quick charge & discharge • RoHS compliant • UL recognized APPLICATIONS • Pulse power demand • Hybrid battery packs • Portable Electronic Devices

35x60

Abstract: 100F 2.7V capacitor TPLS 300F 400F Tecate Industries
Contextual Info: Tecate Group ELECTRIC DOUBLE LAYER SNAP-IN CAPACITOR TYPE TPLS FEATURES • Small size and low-resistance • Quick charge & discharge • RoHS compliant • UL recognized APPLICATIONS • Pulse power demand • Hybrid battery packs • Portable Electronic Devices

Contextual Info: 3-phase brushless motor pre-driver BD63000MUV ●General Description BD63000MUV is pre-driver of 3-phase brushless motor. It generates a driving signal from the Hall sensor and drives PWM through the input control signal. Since there is a built-in booster circuit, Nch-Nch MOS transistors can

BD63005MUV

Contextual Info: Datasheet 3-Phase Brushless Motor Driver BD63005MUV General Description Key Specifications Power supply voltage rating 33V Output current rating Continuous : 2.0A (Note1) A Output current rating (Peak): 3.5 Operating temperature range: -25 to +85°C

C401 diode

Abstract: 10DC IR transistor 10dc ir C4016 C4019 C401 CY7C401 CY7C402 CY7C403 C4013
Contextual Info: CY7C401/CY7C403 CY7C402/CY7C404 64 x 4 Cascadable FIFO 64 x 5 Cascadable FIFO Features words. Both the CY7C403 and CY7C404 have an output enable OE function. • 64 x 4 (CY7C401 and CY7C403) 64 x 5 (CY7C402 and CY7C404) High-speed first-in first-out memory (FIFO)

ups circuit diagram using idvr

Contextual Info: Spansion Analog and Microcontroller Products The following document contains information on Spansion analog and microcontroller products. Although the document is marked with the name “Fujitsu”, the company that originally developed the specification, Spansion

DS14C535MSA

Abstract: MSA28 DS14C335 DS14C535 DS011910-1
Contextual Info: DS14C535 +5V Supply EIA/TIA-232 3 x 5 Driver/Receiver General Description Features The DS14C535 is three driver, five receiver device which conforms to EIA/TIA-232-E and CCITT ITU-T V.28 standard specifications. This device employs an internal DC-DC converter to generate the necessary output levels from a

Contextual Info: Product Folder Sample & Buy Technical Documents Support & Community Tools & Software ADC16DX370 SNVSA18B – APRIL 2014 – REVISED APRIL 2014 ADC16DX370 Dual 16-Bit 370 MSPS ADC With 7.4 Gb/s JESD204B Outputs 1 Features 3 Description • • • • The ADC16DX370 device is a monolithic dualchannel high performance analog-to-digital converter

Contextual Info: Integrated Device Technology, Inc. 32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT FEATURES IDT49C465 IDT49C465A DESCRIPTION 32-bit wide Flow-thruEDC unit, cascadable to 64 bits Single-chip 64-bit Generate Mode Separate system and m em ory buses On-chip pipeline latch with external control

diode pxpr 1002

Abstract: General Electric SCR Manual, Fifth Edition, 1972 hitachi sh7052 hardware manual BOSCH 1 607 502 093 diode pxpr 502 ED06 PJ8 diode TO8B MC15 SH7052
Contextual Info: To all our customers Regarding the change of names mentioned in the document, such as Hitachi Electric and Hitachi XX, to Renesas Technology Corp. The semiconductor operations of Mitsubishi Electric and Hitachi were transferred to Renesas Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog

LR 4100 RELAY

Contextual Info: 58 AM TE-32 ASSP Telecom Standard Product Data Sheet Released r, 20 05 12 :5 3: PM4332 y, 13 De ce m be TE-32 in er In co n Tu es da High Density 32 Channel T1/E1/J1 Framer Proprietary and Confidential Released Issue No. 6: November 2005 Do wn lo ad ed by

Contextual Info: CY7C408A CY7C409A " s CYPRESS SEMICONDUCTOR Features • 64 x 8 and 64 x 9 first-in first-out FIFO buffer memory • 35-MHz shift in and shift out rates • Almost Full/Almost Empty and Half Full flags • Dual-port RAM architecture • Fast (50-ns) bubble-through

Solar Charge Controller mppt ic

Abstract: LTC3625-1 230V ac to 5V dc usb charger circuit Solar Charge Controller mppt maxwell supercapacitor balancing circuit mppt Charge Controller design and circuit mppt ic maxwell supercapacitor mppt chip BCAP120P250
Contextual Info: LTC3625/LTC3625-1 1A High Efficiency 2-Cell Supercapacitor Charger with Automatic Cell Balancing Features Description High Efficiency Step-Up/Step-Down Charging of Two Series Supercapacitors n Automatic Cell Balancing Prevents Capacitor Overvoltage During Charging

SMR 56-7

Abstract: HD64F7051 gr4C gr2b transistor to6 4d SH7051 apc ups schematic HD6437050F20 HD64F7050SF20 HD64F7051SF20
Contextual Info: SH7050 Series Hardware Manual ADE-602-121A Rev. 2.0 3/98 Hitachi, Ltd. MC-Setsu Notice When using this document, keep the following in mind: 1. This document may, wholly or partially, be subject to change without notice. 2. All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the whole

AN-912

Contextual Info: OVERVIEW The scope of this application note is to introduce common data transmission parameters and to provide their definitions. This application note is subdivided into five sections, which are: ample the receiver’s input terminals. This voltage is referenced to circuit common ground . This parameter is illustrated in Figure 1 along with its mathematical equation.

NE5018

Contextual Info: Philips Semiconductors Linear Products Product specification 8-Bit jap-compatible D/A converter NE/SE5018/5019 DESCRIPTION PIN CONFIGURATIONS Ths NE/SE5018/19 is a complete 8-bit digital-to-analog converter subsystem on one monolithic chip. The data inputs have input

C-MAc quartz

Abstract: dth11
Contextual Info: PM I S ta n d a rd P r o d u c t PMC-930303 PMC-Sierra, Inc. I T# ISSUE 4 PM5343STXC SONET/SDH TRANSPORTOVERHEADTRANSCEIVER PM5343 STXC SONET/SDH TRANSPORT OVERHEAD TRANSCEIVER Issue PMC-Sierra, Inc. 4: December 1996 1 0 5 - 8555 Baxter Place Burnaby, BC Canada V5A 4V 7 604 415 6000

Manchester c source code using PIC

Abstract: LF antenna design 24cxx programmer circuit and software 25cxx eeprom programmer circuits 24cxx eeprom tv file AN832C 24cxx eeprom programmer circuits 125KHz LF coil antenna for Automotive AN23-2 Simple Code Hopping Decode
Contextual Info: HCS473 KEELOQ 3-Axis Transcoder FEATURES Package Types PDIP, SOIC Encoder Security Read protected 64-bit encoder key 69-bit transmission length 60-bit, read protected seed for secure learning Programmable 32-bit serial number Non-volatile 16/20-bit synchronization counter

CY7C408A

Abstract: CY7C409A
Contextual Info: 09A CY7C408A CY7C409A 64 x 8 Cascadable FIFO 64 x 9 Cascadable FIFO Features • • • • • • • • • • • 64 x 8 and 64 x 9 first-in first-out FIFO buffer memory 35-MHz shift in and shift out rates Almost Full/Almost Empty and Half Full flags

D07 15

Abstract: 408A2 7C408A-GNDC
Contextual Info: p yp: v « *1 X X CY 7 C 408 A CY 7 C 409 A - 64 x 8 Cascadable FIFO 64 x 9 Cascadable FIFO Features 64 x 8 and 64 x 9 first-in first-out FIFO buffer memory 35-MHz shift in and shift out rates Almost Full/Almost Empty and Half Full flags same order as it was stored on the DO0 - D 0 8 output pins

C40110

Abstract: C401-16
Contextual Info: CY7C401/CY7C403 CY7C402/CY7C404 64 x 4 Cascadable FIFO 64 x 5 Cascadable FIFO Features cading. The output ready OR signal is a flag to indicate the output contains valid data (HIGH), to indicate the FIFO is empty (LOW), and to provide a signal for cascading.

Contextual Info: FUJITSU MICROELECTRONICS DATA SHEET DS07-13729-2E 16-bit Proprietary Microcontroller CMOS F2MC-16LX MB90370 Series MB90372/F372/V370 • DESCRIPTION The MB90370 series is a line of general-purpose, 16-bit microcontrollers designed for those applications which

AN-912

Contextual Info: National Semiconductor Application Note 912 John Goldie October 1993 OVERVIEW The scope of this application note is to introduce common data transmission parameters and to provide their definitions. This application note is subdivided into five sections, which are: