TOGGLE FLIP FLOP Search Results

flip flop T Toggle

Abstract: flip flop T TOGGLE FLIP FLOP
Contextual Info: PSoC Creator Component Datasheet Toggle Flip Flop 1.0 Features • T input toggles Q value • Configurable width for array of Toggle Flip Flops General Description The Toggle Flip Flop captures a digital value that can be toggled. When to Use a Toggle Flip Flop

Contextual Info: P54/74PCT273/A OCTAL D FLIP-FLOP jA - FEATURES • 250MHz Typical Toggle Rate ■ Function, Pinout, Speed and Drive Compatible with

7z93134

Abstract: 74HC 74HCT 7z93131
Contextual Info: 74HC/HCT109 flip-flops D U A L JK FLIP-FLOP W ITH SET A N D RESET; POSITIVE-EDGE TR IG G ER FEATURES • • TYPICAL J, K inputs fo r easy D-type flip -flo p Toggle flip -flo p or "d o nothing" mode O utput capability: standard l£ £ category: flip-flops

Contextual Info: MC14027B Dual J-K Flip-Flop The MC14027B dual J−K flip−flop has independent J, K, Clock C , Set (S) and Reset (R) inputs for each flip−flop. These devices may be used in control, register, or toggle functions. Features • • • • • • • •

Contextual Info: MC14027B Dual J-K Flip-Flop The MC14027B dual J−K flip−flop has independent J, K, Clock C , Set (S) and Reset (R) inputs for each flip−flop. These devices may be used in control, register, or toggle functions. Features • • • • • • • •

14027B

Abstract: HD14027B
Contextual Info: HD14027B Dual J - K Flip Flop The HD14027B dual J-K flip-flop has independent J, K, Clock C , Set(S) and Reset(R) inputs for each flip-flop. These devices may be used in control, register, or toggle functions. • PIN ARRANGEMENT ■ FEATURES • • •

E151

Abstract: SY100EL51ZC SY10EL51 SY10EL51ZC flip-flop 555
Contextual Info: *SYNERGY PRELIMINARY SY10EL51 SY100EL51 DIFFERENTIAL CLOCK D FLIP-FLOP SEMICONDUCTOR FEATURES_ • DESCRIPTION ■ 475ps propagation delay ■ 2.8GHz toggle frequency The SY10EL/100EL51 are differential clock D flip-flops with reset. These devices are functionally sim ilar to the

HCC4027BF

Abstract: HCF4027BE HCC4027B HCF4027B HCF4027BC1 HCF4027BEY HCF4027BM1
Contextual Info: HCC/HCF4027B DUAL-J-K MASTER-SLAVE FLIP-FLOP . . . . . . SET-RESET CAPABILITY STATIC FLIP-FLOP OPERATION - RETAINS STATE INDEFINITELY WITH CLOCK LEVEL EITHER ”HIGH” OR ”LOW” MEDIUM SPEED OPERATION - 16MHz typ. clock toggle rate at 10V STANDARDIZED SYMMETRICAL OUTPUT

HCF4027BE

Abstract: HCF4027BM1 HCC4027B HCC4027BF HCF4027B HCF4027BC1 HCF4027BEY
Contextual Info: HCC/HCF4027B DUAL-J-K MASTER-SLAVE FLIP-FLOP . . . . . . SET-RESET CAPABILITY STATIC FLIP-FLOP OPERATION - RETAINS STATE INDEFINITELY WITH CLOCK LEVEL EITHER ”HIGH” OR ”LOW” MEDIUM SPEED OPERATION - 16MHz typ. clock toggle rate at 10V STANDARDIZED SYMMETRICAL OUTPUT

Contextual Info: ucvnciiD cino HEX D FLIP-FLOP SYNERGY SY100S351 SY1Q1S351 SEMICONDUCTOR PRELIMINARY DESCRIPTION FEATURES • 700 MHz max. Toggle Frequency. The SY100/101S351 offers six D-type, edge-triggered, master/ slave flip-flops with differential outputs, and is designed for use in

CD4027* free

Abstract: 14027B MC14027BCP MC14027BD MC14027BDR2 MC14027BF MC14027BFEL CD4027B MC14027B
Contextual Info: MC14027B Dual J-K Flip-Flop The MC14027B dual J–K flip–flop has independent J, K, Clock C , Set (S) and Reset (R) inputs for each flip–flop. These devices may be used in control, register, or toggle functions. • • • • • • Diode Protection on All Inputs

Contextual Info: MOTOROLA DUAL J-K FLIP-FLOP MC14027B The MC14Q27B dual J-K flip-flop has independent J, K, Clock {Q, Set S and Reset |R) inputs for each flip-flop. These devices may be used in control, register, or toggle functions. CMOS SSI • • Diode Protection on A ll Inputs

MC14027B

Contextual Info: MC14027B Dual J-K Flip-Flop The MC14027B dual J–K flip–flop has independent J, K, Clock C , Set (S) and Reset (R) inputs for each flip–flop. These devices may be used in control, register, or toggle functions. • • • • • • Diode Protection on All Inputs

14027B

Abstract: MC14027B CD4027B MC14027BCP MC14027BD MC14027BDR2 MC14027BF MC14027BFEL
Contextual Info: MC14027B Dual J-K Flip-Flop The MC14027B dual J–K flip–flop has independent J, K, Clock C , Set (S) and Reset (R) inputs for each flip–flop. These devices may be used in control, register, or toggle functions. • • • • • • Diode Protection on All Inputs

HFC4013

Abstract: HCF4013BE HCF4013B HCF4013BEY HFC4013b HCC4013B HCC4013BF HCF4013BC1 HCF4013BM1
Contextual Info: HCC/HCF4013B DUAL ’D’ – TYPE FLIP–FLOP . . . . . . SET-RESET CAPABILITY STATIC FLIP-FLOP OPERATION - RETAINS STATE INDEFINITELY WITH CLOCK LEVEL EITHER ”HIGH” OR ”LOW” MEDIUM-SPEED OPERATION - 16MHz typ. CLOCK TOGGLE RATE AT 10V QUIESCENT CURRENT SPECIFIED TO 20V

HEL51

Contextual Info: SY10EL51 SY100EL51 FINAL DIFFERENTIAL CLOCK D FLIP-FLOP DESCRIPTION FEATURES • ■ ■ ■ 475ps propagation delay 2.8GHz toggle frequency Internal 75KΩ input pull-down resistors Available in 8-pin SOIC package The SY10/100EL51 are differential clock D flip-flops

sd 101k

Contextual Info: TRIPLED FLIP-FLOP ^SYNERGY tVlO lU l] SEMICONDUCTOR ADVANCE INFORMATION FEATURES • ■ 700 MHz max. Toggle Frequency. DESCRIPTION The SY100/101S331 offers three D-type, edge-triggered mas­ ter/slave flip-flops with true and com plem ent outputs, designed

E151

Abstract: SY100EL51 SY100EL51ZC SY10EL51 SY10EL51ZC SY10EL51ZCTR
Contextual Info: SY10EL51 SY100EL51 FINAL DIFFERENTIAL CLOCK D FLIP-FLOP DESCRIPTION FEATURES • ■ ■ ■ 475ps propagation delay 2.8GHz toggle frequency Internal 75KΩ input pull-down resistors Available in 8-pin SOIC package The SY10/100EL51 are differential clock D flip-flops

Single Toggle Flip Flop

Abstract: AT40K AT40KAL AT94K AT94KAL Single T-Type Flip-Flop
Contextual Info: IP Core Generator: Flip-Flop Features • Flip-Flop – D-Type • Flip-Flop – Toggle • Accessible from the Macro Generator Dialog and HDLPlanner – Included in IDS for • • • • • • • • • FPGA Devices and System Designer™ for AT94K FPSLIC™ Devices

Contextual Info: MC14025B See Page 6-5 MOTOROLA MCM025U8 See Page 6-14 MC14027B DUAL J-K FLIP-FLOP The M C14027B dual J-K flip-flop has independent J , K , Clock C , Set (S) and Reset (R ) inputs for each flip-flop. These devices may be used in control, register, or toggle functions.

Contextual Info: * HEX D FLIP-FLOP SYNERGY SEMICONDUCTOR FEATURES DESCRIPTION Max. toggle frequency of 700MHz The SY100S351 offers six D-type, edge-triggered, m aster/slave flip-flops with differential outputs, and is designed for use in high-perform ance ECL system s. The

HFC4013

Abstract: HCF4013BE HCC4013B HFC4013b HCF4013BC HCC4013BF HCF4013B HCF4013BC1 HCF4013BEY HCF4013BM1
Contextual Info: HCC/HCF4013B DUAL ’D’ – TYPE FLIP–FLOP . . . . . . SET-RESET CAPABILITY STATIC FLIP-FLOP OPERATION - RETAINS STATE INDEFINITELY WITH CLOCK LEVEL EITHER ”HIGH” OR ”LOW” MEDIUM-SPEED OPERATION - 16MHz typ. CLOCK TOGGLE RATE AT 10V QUIESCENT CURRENT SPECIFIED TO 20V

MC14027B

Contextual Info: W MOTOROLA D U A L J-K FLIP-FLO P MC14027B The MC14027B dual J-K flip-flop has independent J, K, Clock (Cl, Set ($) and Reset (R) inputs for each flip-flop. These devices may be used in control, register, or toggle functions. • Diode Protection on A ll Inputs

hcf4027be

Abstract: HCF4013B HCF4027B HCF4027BEY HCF4027BM1 HCF4027M013TR
Contextual Info: HCF4027B DUAL J-K MASTER SLAVE FLIP-FLOP • ■ ■ ■ ■ ■ ■ ■ ■ SET RESET CAPABILITY STATIC FLIP-FLOP OPERATION - RETAINS STATE INDEFINETELY WITH CLOCK LEVEL EITHER "HIGH" OR "LOW" MEDIUM-SPEED OPERATION - 16MHz Typ. clock toggle rate at 10V