TKCM Search Results

Contextual Info: ISSI IS61SF6436 64Kx 36 SYNCHRONOUS FLOW-THROUGH STATIC RAM ADVANCE INFORMATION JUNE 1998 FEATURES DESCRIPTION • Fast access times: 8.5 ns, 9 ns, 10 ns The IS S I IS61SF6436 is a high-speed, low-power synchro­ nous static RAM designed to provide a burstable, highperformance, secondary cache for the i486 , Pentium™,

Contextual Info: 64K x 32 LOW VOLTAGE SYNCHRONOUS PIPELINE STATIC RAM ADVANCE INFORMATION MARCH 1997 FEATURES DESCRIPTION • Fast access time: The IS S I IS61LV6432 is a high-speed, low-power synchro­ nous static RAM designed to provide a burstable, highperformance, secondary cache for the Pentium , 680X0™,

Contextual Info: m IS61LV6432 64Kx 32 SYNCHRONOUS PIPELINE STATIC RAM i FEBRUARY 1998 FEATURES DESCRIPTION • Internal self-timed write cycle The IS S IIS61LV6432 is a high-speed, low-power synchro­ nous static RAM designed to provide a burstable, highperformance, secondary cache for the Pentium , 680X0™,

T35L6432B

Abstract: T35L6432B-10Q T35L6432B-12T
Contextual Info: tm TE CH T35L6432B SYNCHRONOUS BURST SRAM 64K x 32 SRAM Flow-Through Burst Mode FEATURES • Fast Access times: 9 / 10 / 11 / 12 ns • Single 3.3V +0.3V/-0.165V power supply • Common data inputs and data outputs • Individual BYTE WRITE ENABLE and GLOBAL WRITE control

Contextual Info: ISSI IS61SP12832 128K x 32 SYNCHRONOUS PIPELINED STATIC RAM ADVANCE INFORMATION MARCH 1998 FEATURES DESCRIPTION • Internal self-timed write cycle TheIS S IIS61SP12832 is a high-speed, low-power synchro­ nous static RAM designed to provide a burstable, highperformance, secondary cache for the Pentium , 680X0™,

Contextual Info: ISSI IS61SF6436 64K x 36 SYNCHRONOUS FLOW-THROUGH STATIC RAM ADVANCE INFORMATION MARCH1997 FEATURES DESCRIPTION • Fast access times: 8.5 ns, 9 ns, 10 ns The IS S IIS61SF6436 is a high-speed, low-power synchro­ nous static RAM designed to provide a burstable, highperformance, secondary cache for the i486 , Pentium™,

Contextual Info: ISSI IS61SF12832 128K x 32 SYNCHRONOUS FLOW-THROUGH STATIC RAM FEATURES • Fast access times: 7.5 ns, 8 ns, 8.5 ns, 10 ns, and 11 ns • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data

Contextual Info: ISSI IS61SP6436 64Kx 36 SYNCHRONOUS PIPELINED STATIC RAM PRELIMINARY DECEMBER 1997 FEATURES DESCRIPTION • Internal self-timed write cycle The IS S IIS61SP6436 is a high-speed, low-power synchro­ nous static RAM designed to provide a burstable, highperformance, secondary cache for the i486 , Pentium™,

Contextual Info: ISSI IS61SF632A 32K x 32 SYNCHRONOUS FLOW-THROUGH FAST STATIC RAM FEATURES • Fast access time: 9 ns, 10 ns • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Pentium or linear burst sequence control

Contextual Info: m t IS61SP25618 256K x 18 SYNCHRONOUS PIPELINED STATIC RAM ADVANCE INFORMATION MAY 1998 FEATURES DESCRIPTION • Internal self-timed write cycle TheIS S IIS61SP25618 is a high-speed, low-power synchro­ nous static RAM designed to provide a burstable, highperformance, secondary cache for the Pentium , 680X0™,

Contextual Info: ISSI IS61LV6464 64Kx 64 SYNCHRONOUS PIPELINE STATIC RAM ADVANCE INFORMATION SEPTEMBER 1997 FEATURES DESCRIPTION • Fast access time: The IS S IIS61LV6464 is a high-speed, low-power synchro­ nous static RAM designed to provide a burstable, highperformance, secondary cache for the Pentium , 680X0™,

T1IG

Abstract: IS61LV6432 D2259
Contextual Info: ISSP 64K x 32 LOW VOLTAGE SYNCHRONOUS PIPELINE STATIC RAM ADVANCE INFORMATION MARCH 1997 FEATURES DESCRIPTION • The IS S IIS61LV6432 is a high-speed, low-power synchro­ nous static RAM designed to provide a burstable, high­ performance, secondary cache for the Pentium , 680X0™,

NS125

Contextual Info: ISSI IS61C632A 32K x 32 SYNCHRONOUS FAST STATIC RAM PRELIMINARY JANUARY 1997 FEATURES DESCRIPTION • Fast access time: The IS S IIS61C632A is a high-speed, low-power synchro­ nous static RAM designed to provide a burstable, highperformance, secondary cache for the i486 , Pentium™,

Contextual Info: IS 6 1 S P 6 4 3 6 64K x 36 SYNCHRONOUS PIPELINED STATIC RAM ADVANCE INFORMATION FEBRUARY 1997 FEATURES DESCRIPTION • Fast access time: The IS61SP6436 is a high-speed, low-power synchro­ nous static RAM designed to provide a burstable, highperformance, secondary cache for the i486 , Pentium™,

Silicon-Based Technology

Contextual Info: SB61S64K64A Silicon-BasedTechnology Ultra High-Speed PBSRAM 64Kx 64 SYNCHRONOUS PIPELINED-BURST CMOS SRAM Preliminary FEATURES: Single 3.3V -5% and +10% power supply Fast clock access time: 3.75ns/133MHz , 4ns/125MHz , 5ns/100MHz Two clocked chip enable/one clocked chip disable

Contextual Info: SB61S128K64A Silicon-BasedTechnology Ultra High-Speed PBSRAM 128Kx 64 SYNCHRONOUS PIPELINED-BURST CMOS SRAM Preliminary FEATURES: Single 3.3V -5% and +10% power supply Fast clock access time: 3.75ns/133MHz , 4ns/125MHz , 5ns/100MHz Two clocked chip enable/one clocked chip disable

Contextual Info: User’s Manual 16 RL78/I1A User’s Manual: Hardware 16-Bit Single-Chip Microcontrollers All information contained in these materials, including products and product specifications, represents information on the product at the time of publication and is subject to change by

Contextual Info: IS61SP6464 64Kx 64 SYNCHRONOUS PIPELINE STATIC RAM FEATURES DESCRIPTION • Fast access time: - PRELIMINARY APRIL 1999 133, 117, 100 MHz; 6 ns 83 MHz ; 7 ns (75 MHz); 8 ns (66 MHz) • Internal self-tim ed w rite cycle • Individual Byte W rite Control and Global W rite

Contextual Info: I S 6 1 S P 1 2 8 3 2 128K x 32 SYNCHRONOUS PIPELINED STATIC RAM ADVANCE INFORMATION APRIL 1999 FEATURES DESCRIPTION • In te rn a l s e lf-tim e d w rite c y c le • In d iv id u a l B y te W rite C o n tro l a n d G lo b a l W rite T h e lS S I IS 61SP12832 is a high-speed, low -pow er syn chro ­

Contextual Info: ISSI IS 61S P 6436 64Kx 36 SYNCHRONOUS PIPELINED STATIC RAM FEATURES DESCRIPTION • Internal self-tim ed w rite cycle • Individual Byte W rite Control and Global W rite • C lock controlled, registered address, data and control • Pentium or linear burst sequence control

ir tk 69

Contextual Info: IS61LV632A 32K x 32 SYNCHRONOUS FAST STATIC RAM PRELIMINARY MAY 1998 FEATURES DESCRIPTION • Fast access time: The IS S IIS61LV632A is a high-speed, low-power synchro­ nous static RAM designed to provide a burstable, highperformance, secondary cache for the i486 , Pentium™,

Contextual Info: I S 6 1 Z B ISSI 1 2 8 3 6 128K x 36 SYNCHRONOUS STATIC RAM ZERO TURNAROUND BUS AND PIPELINE ADVANCE INFORMATION FEBRUARY 1998 FEATURES DESCRIPTION • 100 percent bus utilization The IS61ZB12836 is a high-speed, low-power synchronous static RAM designed to provide a burstable, highperformance, zero turnaround bus, secondary cache for the

Contextual Info: WM IS 6 1 S P 1 2 8 3 6 128K x 36 SYNCHRONOUS PIPELINED STATIC RAM ADVANCE INFORMATION JUNE 1998 FEATURES DESCRIPTION T h e I S S I IS61SP12836 is a high-speed, low-power synchro­ nous static RAM designed to provide a burstable, highperformance, secondary cache for the i486 , Pentium™,

Contextual Info: MOSEL VITELIC V54C328804VC HIGH PERFORMANCE 143/133/125MHz 3.3 VOLT 16M X 8 SYNCHRONOUS DRAM 4 BANKS X 4Mbit X 8 PRELIMINARY 7 75 8 System Frequency fCK 143 MHz 133 MHz 125 MHz Clock Cycle Time (tcK3 ) 7 ns 7.5 ns 8 ns Clock Access Time (tAC3) CAS Latency = 3