THREE INPUT OR GATE Search Results

Contextual Info: C2MOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC TC4071BP/BF/BFNJC4072BP/BF TC4075BP/BF TC4071B QUAD 2 INPUT OR GATE TC4072B DUAL 4 INPUT OR GATE TC4075B TRIPLE 3 INPUT OR GATE TC4071B, TC4075BP / BF and TC4072BP / BF are positive logic OR gates w ith tw o inputs, three inputs and fo ur inputs

CMOS 4000 Logic Family

Abstract: MN74HC4075 MN74HC4075S CMOS 4000 4000 series Cmos logic gate
Contextual Info: High-Speed CMOS Logic MN74HC Series m N 74H C 4075/ aaN74HC4075S MN74HC4075 MN74HC4075S Triple 3-Input OR Gates • P-1 Description MN74HC4075/MN74HC4075S contain three 3 -input positive isolation OR gate circuits. Adoption o f a silicon gate CMOS process has resulted in low

Hitachi DSA0095

Abstract: HD74HC32 HD74UH32
Contextual Info: HD74UH32 2-input OR Gate ADE-205-018B Z 3rd. Edition Sep. 2000 Description The HD74UH32 is high speed CMOS two input OR gate using silicon gate CMOS process. With CMOS low power dissipation, it provides high speed equivalent to LS-TTL series. The internal circuit of three

Hitachi DSA00279

Contextual Info: HD74UH32 2-input OR Gate The HD74UH32 is high speed CMOS two input OR gate using silicon gate CMOS process. With CMOS low power dissipation, it provides high speed equivalent to LS-TTL series. The internal circuit of three stages construction with buffer provides wide noise margin and stable output.

DALE R 01F

Abstract: oms 450 R9810 CON-DB25HF DRB2 OMS 1410 CRCW1206000ZT ITT Cannon ITT Cannon SMB Connectors AD8055
Contextual Info: a FEATURES 140 MSPS Guaranteed Conversion Rate 100 MSPS Low Cost Version Available 330 MHz Analog Bandwidth 1 V p-p Analog Input Range Internal +2.5 V Reference Differential or Single-Ended Clock Input 3.3 V/5.0 V Three-State CMOS Outputs Single or Demultiplexed Output Ports

CON-DB25HF

Abstract: CRCW1206000ZT oms 450 AD8055 AD9483 AD9483KS-100 AD9483KS-140 R101 R102 so20w
Contextual Info: a FEATURES 140 MSPS Guaranteed Conversion Rate 100 MSPS Low Cost Version Available 330 MHz Analog Bandwidth 1 V p-p Analog Input Range Internal +2.5 V Reference Differential or Single-Ended Clock Input 3.3 V/5.0 V Three-State CMOS Outputs Single or Demultiplexed Output Ports

DM74S11

Abstract: DM54S11J DM54S11W DM74S11N J14A N14A W14B
Contextual Info: DM74S11 Triple 3-Input AND Gates General Description This device contains three independent gates each of which performs the logic AND function. Connection Diagram Dual-In-Line Package DS006447-1 Order Number DM54S11J, DM54S11W or DM74S11N See Package Number J14A, N14A or W14B

DM74S10

Abstract: DM54S10J DM54S10W DM74S10N J14A N14A W14B
Contextual Info: DM74S10 Triple 3-Input NAND Gates General Description This device contains three independent gates each of which performs the logic NAND function. Connection Diagram Dual-In-Line Package DS006446-1 Order Number DM54S10J, DM54S10W or DM74S10N See Package Number J14A, N14A or W14B

C3601

Abstract: AD774x AD7741 AD7741BN AD7741BR AD7741YR AD7742 AD7742BN AD7742BR AD7742YR
Contextual Info: a Single and Multichannel, Synchronous Voltage-to-Frequency Converters AD7741/AD7742 FEATURES AD7741: One Single-Ended Input Channel AD7742: Two Differential or Three Pseudo-Differential Input Channels Integral Nonlinearity of 0.012% at fOUT Max = 2.75 MHz

Contextual Info: a Single and Multichannel, Synchronous Voltage-to-Frequency Converters AD7741/AD7742 FEATURES AD7741: One Single-Ended Input Channel AD7742: Two Differential or Three Pseudo-Differential Input Channels Integral Nonlinearity of 0.012% at fOUT Max = 2.75 MHz

C1995

Abstract: DM54L10 DM54L10J DM54L10W J14A W14B
Contextual Info: DM54L10 Triple 3-Input NAND Gates General Description This device contains three independent gates each of which performs the logic NAND function Connection Diagram Dual-In-Line Package TL F 6619 – 1 Order Number DM54L10J or DM54L10W See NS Package Number J14A or W14B

Contextual Info: MC74VHC1G86 Single 2-Input Exclusive OR Gate The MC74VHC1G86 is an advanced high speed CMOS 2−input Exclusive OR gate fabricated with silicon gate CMOS technology. The internal circuit is composed of three stages, including a buffer output which provides high noise immunity and stable output.

A114

Abstract: A115 C101 JESD22 MC74VHC1G86 VHC1G00 SC88A MC 68 H 705
Contextual Info: MC74VHC1G86 Single 2-Input Exclusive OR Gate The MC74VHC1G86 is an advanced high speed CMOS 2–input Exclusive OR gate fabricated with silicon gate CMOS technology. The internal circuit is composed of three stages, including a buffer output which provides high noise immunity and stable output.

F10210

Abstract: F10211 F10610 F10611
Contextual Info: F10210 F10211l/» F10610"* F10611 DUAL 3-3 OR • DUAL 3-3 NOR FlOK VOLTAGE COMPENSATED ECL GENERAL DESCRIPTION — The F10210 and F10610 are Dual 3-Input 3-O utput OR Gates and the F10211 and F10611 are Dual 3-Input 3-O utput NOR Gates. Each gate has three output transistors driven in parallel, with their emitters brought out on

54F64

Abstract: GDFP1-F14
Contextual Info: Product specification Philips Semiconductors Military FAST Products Four-two-three-two-input AND-OR-invert gate 54F64 ORDERING INFORMATION DESCRIPTION ORDER CODE PACKAGE DESIGNATOR* 14-Pin Ceramic DIP 54F64/BCA GDIP1-T14 14-Pin Ceramic Flat Pack 54F64/BDA

HCC4076B

Abstract: HCC4076BF HCF4076B HCF4076BC1 HCF4076BEY HCF4076BM1
Contextual Info: HCC4076B HCF4076B 4 BIT D TYPE REGISTERS . . . . . THREE STATE OUTPUTS INPUT DISABLE WITHOUT GATING THE CLOCK GATED OUTPUT CONTROL LINES FOR ENABLING OR DISABLING THE OUTPUTS QUIESCENT CURRENT SPECIFIED TO 20V FOR HCC DEVICE 5V, 10V AND 15V PARAMETRIC RATINGS

DM54LS15J

Abstract: DM54LS15W DM74LS15M DM74LS15N J14A M14A N14A W14B
Contextual Info: & May 1992 DM54LS15/DM74LS15 Triple 3-Input AND Gate with Open-Collector Outputs General Description This device contains three independent gates, each of which perform the logic AND function. The outputs are open-collect or. Connection Diagram Dual-In-Line Package

chn 547

Abstract: chn 808 MPS 1012 chn 940 MPS 1005 HDAS-16 HDAS-16MC MX-1606 HDAS8MM 3000 watt inverter circuit diagram
Contextual Info: HDAS-16, HDAS-8 12-Bit, 50kHz, Complete Data Acquisition Systems FEATURES Miniature 62-pin cermanic package 12-Bit resolution, 50kHz throughput Full-scale input range from 50mV to 10V Three-state outputs 16 S.E. or 8 differential input channels Auto-sequencing channel addressing

Contextual Info: ANALOG D E V IC E S Single and Multichannel, Synchronous Voltage-to-Frequency Converters AD7741/AD7742 FEATURES AD7741: One Single-Ended Input Channel AD7742: Tw o Differential or Three Pseudo-Differential Input Channels Integral N onlinearity of 0.012% at f0ui M ax = 2.75 MHz

Contextual Info: GD54/74S10 TRIPLE 3-INPUT POSITIVE NAND GATES Description Pin Configuration This device contains three independent 2-input NAND gates. It performs the Boolean functions Y = A .B .C or Y=A+"BVC in positive logic. Vcc m 1C hi 1Y 3C 3B n^i rn h°ì 3A fi 3Y rn

74LS11 pin configuration

Contextual Info: GD54/74LS11 TRIPLE 3-INPUT POSITIVE AND GATES Description Pin Configuration This device contains three independent 3-input AND gates. It performs the Boolean functions Y = A B C or Y = A + B + C in positive logic. Vcc 1C 1Y 3C 36 3A 3Y 14 13 12 11 10 9 8 Function Table each gate

A 3020 8 pin

Abstract: 10 Hz oscillator 3020 transistor power supply TA 3020
Contextual Info: ADVANCED ANALOG A D iv is io n o f intech 3020 DESCRIPTION The 3020 m onolithic integrated circuit includes three LED/lamp drivers. Each of the three drivers has two TTL com patible inputs. When the first input is set low, the output is turned ON causing an LED or lamp to turn on.

l6386d

Abstract: STTH1L06U STEVAL-IHM011V1 resistor 220r 1W BAR43FILM STG3P2M10N60B TS374ID TSH24ID resistor 1K 5w R21 BH SMD
Contextual Info: STEVAL-IHM011V1 IGBT power module kit - SEMITOP2 power board Data Brief Features • 34-pin dedicated motor control connector ■ 5-pins hall sensor/encoder input ■ Tachometer sensor input ■ Support for 5 V or 3.3 V microcontroller ■ Three configurations for current detection:

SU53

Abstract: B-05
Contextual Info: Am2927/Am2928 Am2927/Am2928 Quad Three-State Bus Transceivers With Clock Enable DISTINCTIVE CHARACTERISTICS Output data to input wrap around gating; Input register to output transfer gating with or without driving data bus Clock enabled registers 3.0V minimum Vqh for direct interface to MOS micro­