DM74S11 Search Results

DM74S112

Abstract: DM54S112 DM54S112J DM74S112N J16A N16E
Contextual Info: DM74S112 Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Preset, Clear, and Complementary Outputs sition time of the negative going edge of the clock pulse. Data on the J and K inputs can be changed while the clock is high or low without affecting the outputs as long as setup

74s112n

Abstract: 54S112 74S112
Contextual Info: I R C H I L D S E M I C O N D U C T O R TM DM74S112 Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Preset, Clear, and Complementary Outputs General Description sition tim e of th e negative going edge o f the clock pulse. Data on the J and K inputs can be changed w hile the clock

C1995

Abstract: DM54S112 DM54S112J DM74S112 DM74S112N J16A N16E
Contextual Info: DM54S112 DM74S112 Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Preset Clear and Complementary Outputs General Description This device contains two independent negative-edge-triggered J-K flip-flops with complementary outputs The J and K data is processed by the flip-flops on the falling edge of

preset 100 K

Abstract: DM54S112 DM54S112J DM74S112 DM74S112N J16A N16E
Contextual Info: , June 1989 DM54S112/DM74S112 Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Preset, Clear, and Complementary Outputs General Description This device contains two independent negative-edge-trig­ gered J-K flip-flops with complementary outputs. The J and

DM54

Abstract: DM74 DM74S114
Contextual Info: ÆjA Semiconductor DM54S114/DM74S114 Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Preset, Common Clear, Common Clock and Complementary Outputs General Description Absolute Maximum Ratings Note d T h is d e v ic e c o n ta in s tw o n e g a tiv e -e d g e -trig g e re d J-K

Contextual Info: S E M IC O N D U C T O R tm DM74S11 Triple 3-Input AND Gates General Description This device contains three independent gates each of which perform s the logic AN D function. Connection Diagram 3 Ai Y3 1 Y1 c3 B Vet. C 13 12 1 1 1 9 8 D jal-ln-Lin e Packa ge

DM74S11

Abstract: DM54S11J DM54S11W DM74S11N J14A N14A W14B
Contextual Info: DM74S11 Triple 3-Input AND Gates General Description This device contains three independent gates each of which performs the logic AND function. Connection Diagram Dual-In-Line Package DS006447-1 Order Number DM54S11J, DM54S11W or DM74S11N See Package Number J14A, N14A or W14B

74S112

Abstract: 54 dual JK fairchild
Contextual Info: Revised April 2000 DM74S112 Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Preset, Clear, and Complementary Outputs General Description This device contains two independent negative-edge-triggered J-K flip-flops with complementary outputs. The J and

Contextual Info: S E M IC O N D U C T O R tm DM74S11 Triple 3-Input AND Gates General Description This device contains three independent gates each of which performs the logic AND function. Connection Diagram D jal-ln-Lin e Packa 3 Va. Y1 C lM Ai B3 c3 11 12 13 Y3 9 1 1

DM54S11

Abstract: DM54S11W DM74S11N J14A N14A W14B
Contextual Info: , June 1989 DM54S11/DM74S11 Triple 3-Input AND Gates General Description This device contains three independent gates each of which performs the logic AND function. Connection Diagram Dual-In-Line Package V, , U1 VI C3 B3 A3 Y3 Order Number DM54S11J, DM54S11W or DM74S11N

Contextual Info: ¡^National Semiconductor DM54S11/DM74S11 Triple 3-Input AND Gates General Description This device contains three independent gates each of which performs the logic AND function. Connection Diagram Dual-ln-Line Package Y1 C3 B3 A3 3 D -1 Order Number DM54S11J, DM54S11W or DM74S11N

Contextual Info: Ju n e 1989 Semiconductor DM54S113/DM74S113 Dual N egative-Edge-Triggered M aster-Slave J-K Flip-Flops with Preset and C om plem en tary O utputs General Description T h is d evice co ntain s tw o in d epen d ent negative-edge-trig­ gered J - K flip-flops with co m p lem entary outputs. T h e J and

DM74S11

Abstract: DM74S11N MS-001 N14A
Contextual Info: Revised April 2000 DM74S11 Triple 3-Input AND Gate General Description This device contains three independent gates each of which performs the logic AND function. Ordering Code: Order Number DM74S11N Package Number N14A Package Description 14-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, 0.300 Wide

DM54

Abstract: DM54S11 DM54S11W DM74S11 DM74S11N J14A N14A W14B
Contextual Info: National Semiconductor DM54S11/DM74S11 Triple 3-Input AND Gates General Description This device contains three independent gates each of which performs the logic AND function. Connection Diagram □ual-ln-Line Package T L /F /6 4 4 7 -1 Order Number DM54S11J, DM54S11W or DM74S11N

Contextual Info: June 1989 DM54S112/DM74S112 Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Preset, Clear, and Complementary Outputs General Description This device contains two independent negative-edge-trig­ gered J-K flip-flops with complementary outputs. The J and

Contextual Info: June 1989 DM54S11/DM74S11 Triple 3-Input AND Gates General Description This device contains three independent gates each of which performs the logic AND function. Connection Diagram Dual-In-Line Package V,:r U1 VI C3 B3 A3 Y3 Order Number DM54S11J, DM54S11W or DM74S11N

DM74S112N

Abstract: DM54S112 DM54S112J DM74S112 J16A N16E
Contextual Info: DM74S112 Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Preset, Clear, and Complementary Outputs sition tim e o f th e negative going edge o f the clock pulse. Data on the J and K inputs can be changed w hile the clock is high o r low w ithout affecting the outputs as long as setup

DM74S113N

Abstract: C1995 DM54S113 DM54S113J DM74S113 J14A N14A
Contextual Info: DM54S113 DM74S113 Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Preset and Complementary Outputs General Description This device contains two independent negative-edge-triggered J-K flip-flops with complementary outputs The J and K data is processed by the flip-flops on the falling edge of

Contextual Info: S112 National Semiconductor DM54S112/DM74S112 Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Preset, Clear, and Complementary Outputs General Description This device contains two independent negative-edge-trig­ gered J-K flip-flops with complementary outputs. The J and

DM54S113

Abstract: DM54S113J DM74S113 DM74S113N J14A N14A
Contextual Info: DM54S113/DM74S113 Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Preset and Complementary Outputs General Description This device contains two independent negative-edge-trig­ gered J-K flip-flops with complementary outputs. The J and K data is processed by the flip-flops on the falling edge of

J14A

Abstract: N14A W14B DM54S11J DM54S11W DM74S11 DM74S11N
Contextual Info: S E M IC O N D U C T O R tm DM74S11 Triple 3-Input AND Gates General Description This device contains three independent gates each of which perform s the logic A N D function. Connection Diagram Dual-ln-Line Package DS006447-1 Order Number DM54S11J, DM54S11W or DM74S11N

DM74S112

Abstract: MS-001 N16E
Contextual Info: Revised April 2000 DM74S112 Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Preset, Clear, and Complementary Outputs General Description This device contains two independent negative-edge-triggered J-K flip-flops with complementary outputs. The J and

DM74S112

Abstract: MS-001 N16E
Contextual Info: Revised April 2000 DM74S112 Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Preset, Clear, and Complementary Outputs General Description This device contains two independent negative-edge-triggered J-K flip-flops with complementary outputs. The J and

Contextual Info: S112 National Semiconductor DM54S112/DM74S112 Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Preset, Clear, and Complementary Outputs General Description This device contains two independent negative-edge-triggered J-K flip-flops with complementary outputs. The J and