TDRC Search Results

Contextual Info: 1CT i 1CT J1 J2 J3 J4 J5 J6 J7 J8 TD+ TDRCT rd- P 6 ch a s s is g n d (P 8 lOOOpF, 2KV RX- NDTES 1.0 CDMPLIES WITH THE EURDPEAN D IR E C T IV E 2 0 0 2 / 9 5 / E C , CALLING FDR THE ELIMINATION DF LEAD AND EITHER HAZARDOUS SUBSTANCES FRDM ELECTRONIC PRDDUCTS,

Contextual Info: 1CT : 1CT J1 J2 J3 J4 J5 J6 J7 J8 TD+ TDRCT TX + TXRX+ RX- lOOOpF, 2 K V NDTES 1,0 PINS WITHDUT E L E C T R I C A L CDNNECTIDN ARE DMITTED, ELECTRICAL SPECIFICATIONS: OPERATING TEMPERATURE RANGE: -40'C TO + 8 5 ’ C 1.0 TURNS RATIO: P 4 - P 5 - P 6 : (J 3 - J 6 )

Contextual Info: 1CT i 1CT J1 J2 J3 J4 J5 J6 J7 J8 TD+ TDRCT rd- P 6 ch a s s is g n d (P 8 lOOOpF, 2KV RX- NDTES 1.0 CDMPLIES WITH THE EURDPEAN D I R E C T I V E 2 0 0 2 / 9 5 / E C , CALLING FDR THE ELIMINATION DF LEAD AND EITHER HAZARDOUS SU BSTANCES FRDM ELECTRONIC PRDDUCTS,

Contextual Info: 1CT i 1CT J1 J2 J3 J4 J5 J6 J7 J8 TD+ TDRCT rd- P 6 c h a s s is g n d ( P 8 lOOOpF, 2 K V 1.0 CDMPLIES WITH THE EURDPEAN D I R E C T I V E 2 0 0 2 / 9 5 / E C , CALLING FDR THE ELIMINATION DF LEAD AND EITHER HAZARDOUS SU BSTANCES FRDM ELECTRONIC PRDDUCTS,

50087

Abstract: 708117
Contextual Info: 1CT : 1CT J1 J2 J3 J4 J5 J6 J7 J8 TD+ TDRCT rd- P 6 CHASSIS GN d ( P 8 ) - TX+ TXRX+ RX- lOOOpF, 2 K V NDTES ELECTRICAL SPECIFICATIONS: 1,0 PINS WITHDUT E L E C T R I C A L CDNNECTIDN ARE DMITTED, 1.0 TURNS RATIO ( P 4 - P 5 - P 6 ) : ( J 3 - J 6 ) (P 3 -P 2 -P 1 ) : (J 1 -J 2 )

56531

Contextual Info: DG485 Octal Analog Switch Array Features Benefits Applications • • • • • • • Low Signal Distortion • Devices Can Be Chained for System Expansion • Reduced Board Space • Reduced Switch Errors • Reduced Power Supply Requirements • Simple Interfacing

100-BT

Contextual Info: TLK100 www.ti.com SLLS931B – AUGUST 2009 – REVISED DECEMBER 2009 Industrial Temp, Single Port 10/100 Mb/s Ethernet Physical Layer Transceiver Check for Samples: TLK100 1 Introduction 1.1 Features 1 • • • • • • • • • • • • Temperature From –40°C to 85°C

IEEE1588

Abstract: VD11
Contextual Info: TLK100 www.ti.com SLLS931B – AUGUST 2009 – REVISED DECEMBER 2009 Industrial Temp, Single Port 10/100 Mb/s Ethernet Physical Layer Transceiver Check for Samples: TLK100 1 Introduction 1.1 Features 1 • • • • • • • • • • • • Temperature From –40°C to 85°C

Contextual Info: Component Development Environment CDE User Guide Revised: 17 January 2013 Freescale, the Freescale logo, CodeWarrior, ColdFire, ColdFire+, Kinetis, Processor Expert, and Qorivva are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. All other product or service names are the property

HV633

Abstract: HV633PG HV633PG-G
Contextual Info: HV633 32-Channel, 128-Level Amplitude Gray-Shade Display Column Driver Features General Description ► ► ► ► ► ► ► ► ► The HV633 is a 32-channel driver IC for gray shade display use. It is designed to produce varying output voltages between

Contextual Info: EM78P210N 8-Bit Microcontroller with OTP ROM Product Specification DOC. VERSION 1.3 ELAN MICROELECTRONICS CORP. April 2013 Trademark Acknowledgments: IBM is a registered trademark and PS/2 is a trademark of IBM. Windows is a trademark of Microsoft Corporation.

9LPRS501

Abstract: CK505 72 pin 9LPRS501SGLF ck505
Contextual Info: Datasheet ICS9LPRS501 64-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR + INTEGRATED SERIES RESISTOR Recommended Application: Key Specifications: CK505 compliant clock with fully integrated voltage regulator and Internal series resistor on differential outputs,

ph82

Abstract: ph84 PL83 EM78P350N EM78P350NK EM78P350NM EM78P350NP PH67
Contextual Info: EM78P350N 8-Bit Microprocessor with OTP ROM Product Specification DOC. VERSION 1.0 ELAN MICROELECTRONICS CORP. September 2006 Trademark Acknowledgments: IBM is a registered trademark and PS/2 is a trademark of IBM. Windows is a trademark of Microsoft Corporation.

transistor bl p89

Abstract: bl p74 transistor J955 XC4000 XC4000A XC4000D XC4000E XC4000EX XC4000H p180 g8
Contextual Info: book XC4000E and XC4000X Series Field Programmable Gate Arrays R January 29, 1999 Version 1.5 6* XC4000E and XC4000X Series Features Note: XC4000 Series devices described in this data sheet include the XC4000E family and XC4000X Series. XC4000X Series devices described in this data sheet

4046 FSK

Abstract: BELL212A ST18933 ST7544 ST75C502 TQFP44 TQFP80 tdt7 ST TX01
Contextual Info: ST75C502 V.32bis/V.17 HIGH SPEED MODEM DATA PUMP . . . . . . . . . . . . 2 CHIP DATA PUMP ST75C502, ST7544 V.32BIS, V.17, V.33, V.32, V.29, V.27ter, V.22BIS, V.22, V.21, V.23, BELL212A, 103 (SHORT TRAIN INCLUDING V.29/T104) GROUP 3 FAX AT 14400, 12000, 9600, 7200,

VG-4231CA

Contextual Info: Product Configuration System Oscillators - VCXO VG 4231CA VG‐4231CA 75.0000M

window alarm 323H

Abstract: B772 031 B765 TCA 365H b772 p B788 AW 136H E1 HDB3 128-PIN PQFP 38Dh
Contextual Info: PM7344 S/UNI-MPH DATA SHEET PMC-950449 ISSUE 6 MULTI-PHY USER NETWORK INTERFACE PM7344 TM S/UNI- MPH S/UNI-MPH SATURN QUAD T1/E1 MULTI-PHY USER NETWORK INTERFACE DEVICE DATA SHEET ISSUE 6: JUNE 1998 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

LC 21 B

Contextual Info: HV633 HV633 Preliminary 32-Channel 128-Level Amplitude Gray-Shade Display Column Driver Features General Description ❏ 5V CMOS inputs The HV633 is a 32-channel driver IC for gray shade display use. It is designed to produce varying output voltages between 3 and

pec 730

Abstract: 9LP525BF-2LF desktop board crb
Contextual Info: DATASHEET 56-pin CK505 for Intel Desktop Systems Recommended Application: CK505 clock, 56-pin Intel Yellow Cover part Output Features: • 2 - CPU differential low power push-pull pairs • 7- SRC differential low power push-pull pairs • 1 - CPU/SRC selectable differential low power push-pull pair

ttl 7492

Abstract: 74912 7490 pin diagram 7490 mod 16 chip 7490 TTL 7490 data 7492 pin out diagram C108H
Contextual Info: PRELIMINARY CYM7490 CYM7491 CYM7492 i486 Level II Cache Module Family Features Functional Description • Cache sizes of 64 KB, 256 KB, or 1 MB • Tag width of 8 bits • Independent dirty bit • Operates with 33-MHz Intel ¡486 processors • Zero-wait-state operation

GG1Q

Contextual Info: 1.0 Product Description 1.1 Introduction Figure 1-1 is a detailed block diagram o f the Bt8222. For transmission from the host system, octet-wide data is input from the UTOPIA or FIFO ports. The host data is assembled into ATM cells and then formatted for serial line transmission

Contextual Info: ¿ 7 7 * J Æ , S C S -T H O M S O N ST75C52 l i! S O g lB i ll l i® ¥ l s ! ® H B @ § HIGH SPEED FAX MODEM DATA PUMP • ITU-T V.17, V.29, V.27ter, V.21 WITH FAX SUPPORT ■ ITU-T V.23, V.21, BELL 103 ■ V.17, V.29 (T104 , V.27ter SHORT TRAINS ■ V.33 HALF-DUPLEX

Contextual Info: r = J S G S -T tfO M S O N ST5451 ISDN HDLC AND GCI CONTROLLER A D V A N C E DATA . • ■ ■ ■ . . ■ MONOLITHIC ISDN ORIENTED HDLC AND GCI CONTROLLER. GCI AND |iW/DSI COMPATIBLE. FULLY CONTROLLING GCI AND GCI-SCIT M & C/I CHANNELS MANAGEMENT. FULLY SUPPORTING LAPB AND LAPD

Contextual Info: S3C2800 32-BIT RISC MICROPROCESSOR USER'S MANUAL Revision 1.2 Important Notice The information in this publication has been carefully checked and is believed to be entirely accurate at the time of publication. Samsung assumes no responsibility, however, for possible