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    TDC 410 Search Results

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    TDC 410 Price and Stock

    OMRON Corporation

    OMRON Corporation G3NA-410B-UTU DC5-24

    Solid State Relays - SSRs Solid State Relay
    Distributors Part Package Stock Lead Time Min Order Qty Price Buy
    Mouser Electronics G3NA-410B-UTU DC5-24
    • 1 $102.51
    • 10 $98.09
    • 100 $93.31
    • 1000 $93.31
    • 10000 $93.31
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    TDC 410 Datasheets Context Search

    Catalog Datasheet Type Document Tags PDF

    pdc156

    Abstract: J17H
    Contextual Info: DIRECTIONAL COUPLERS 50 & 75Ω Plug-In 6 to 30 dB COUPLING up to 10W 5 kHz to 2000 MHz TDC MODEL NO. TDC-6-1 TDC-10-1 TDC-10-2 FREQ. RANGE MHz fL-fU COUPLING dB Nom. MAINLINE LOSS dB L Flatness Typ. Max. 6.3±0.4 10.0±0.5 11.0±0.5 ±0.4 ±0.5 ±0.6 2.0


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    PDC-20A-5 TDC-10-1 TDC-10-2 PDC-10-1 PDC-10-2 PDC-10-5 PDC-10-6 PDC-10-21* PDC-10-22 PDC-10-54 pdc156 J17H PDF

    TDC+410

    Abstract: TDC 410 216CO2 AD10 AD11 AD12 AD14
    Contextual Info: CUSTOMER PROCUREMENTSPECIFICATION 216COl/CO2 CPUCENTRALPROCESSINGUNIT FEATURES Part Zi 6COl Z16CO2 Memory Address 8 Mbytes 64 Kbytes Memory Extension 48 Mbytes 384 Kbytes Speed MHz 10 10 H Extendable Register Files 1 Nine Basic Instruction Types n 40/48-Pin PDIP and 44-Pin PLCC Packages’


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    216COl/CO2 Z16CO2 40/48-Pin 44-Pin Z16COl/CO2 16-bit O-338-7821 TDC+410 TDC 410 216CO2 AD10 AD11 AD12 AD14 PDF

    A12L

    Abstract: A13L CY7C09159A CY7C09169A
    Contextual Info: 25/0251 CY7C09159A CY7C09169A 8K/16K x 9 Synchronous Dual-Port Static RAM Features • True dual-ported memory cells which allow simultaneous access of the same memory location • Two Flow-Through/Pipelined devices — 8K x 9 organization CY7C09159A — 16K x 9 organization (CY7C09169A)


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    CY7C09159A CY7C09169A 8K/16K CY7C09159A) CY7C09169A) 100-MHz 35-micron A12L A13L CY7C09159A CY7C09169A PDF

    TDC 410

    Abstract: A12L CY7C09349A CY7C09359A
    Contextual Info: 25/0251 CY7C09349A CY7C09359A 4K/8K x 18 Synchronous Dual-Port Static RAM Features • True dual-ported memory cells which allow simultaneous access of the same memory location • Two Flow-Through/Pipelined devices — 4K x 18 organization CY7C09349A — 8K x 18 organization (CY7C09359A)


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    CY7C09349A CY7C09359A CY7C09349A) CY7C09359A) 100-MHz 35-micron CY7C09349A/CY7C09359A TDC 410 A12L CY7C09349A CY7C09359A PDF

    A12L

    Abstract: A13L CY7C09159A CY7C09169A
    Contextual Info: 25/0251 CY7C09159A CY7C09169A 8K/16K x 9 Synchronous Dual-Port Static RAM Features • True dual-ported memory cells which allow simultaneous access of the same memory location • Two Flow-Through/Pipelined devices — 8K x 9 organization CY7C09159A — 16K x 9 organization (CY7C09169A)


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    CY7C09159A CY7C09169A 8K/16K CY7C09159A) CY7C09169A) 100-MHz 35-micron CY7C09159A/CY7C09169A A12L A13L CY7C09159A CY7C09169A PDF

    A12L

    Abstract: CY7C09349A CY7C09359A ind-510
    Contextual Info: 1 CY7C09349A CY7C09359A PRELIMINARY 4K/8K x 18 Synchronous Dual-Port Static RAM Features • True dual-ported memory cells which allow simultaneous access of the same memory location • Two Flow-Through/Pipelined devices — 4K x 18 organization CY7C09349A


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    CY7C09349A CY7C09359A CY7C09349A) CY7C09359A) 100-MHz 35-micron A12L CY7C09349A CY7C09359A ind-510 PDF

    IDT709269

    Abstract: IDT709279
    Contextual Info: fax id: 5217 51 CY7C09269/79/89 CY7C09369/79/89 PRELIMINARY 16K/32K/64K x16/18 Synchronous Dual Port Static RAM Features • True Dual-Ported memory cells which allow simultaneous access of the same memory location • 6 Flow-Through/Pipelined devices — 16K x 16/18 organization CY7C09269/369


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    CY7C09269/79/89 CY7C09369/79/89 16K/32K/64K x16/18 CY7C09269/369) CY7C09279/379) CY7C09289/389) IDT709269 IDT709279 PDF

    78R15

    Abstract: IDT709279
    Contextual Info: 1 CY7C09279/89 CY7C09379/89 32K/64K x16/18 Synchronous Dual Port Static RAM Features • True dual-ported memory cells which allow simultaneous access of the same memory location • Six Flow-Through/Pipelined devices — 32K x 16/18 organization CY7C09279/379


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    CY7C09279/89 CY7C09379/89 32K/64K x16/18 CY7C09279/379) CY7C09289/389) 100MHz 35-micron 78R15 IDT709279 PDF

    Contextual Info: 25/0251 CY7C09159A CY7C09169A 8K/16K x 9 Synchronous Dual-Port Static RAM Features • True dual-ported memory cells which allow simultaneous access of the same memory location • Two Flow-Through/Pipelined devices — 8K x 9 organization CY7C09159A — 16K x 9 organization (CY7C09169A)


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    CY7C09159A CY7C09169A 8K/16K CY7C09159A) CY7C09169A) 100-MHz 35-micron CY7C09159A/CY7C09169A PDF

    IDT709079

    Abstract: IDT709089
    Contextual Info: 1 CY7C09079A/89/99 CY7C09179A/89/99 PRELIMINARY 32K/64K/128K x 8/9 Synchronous Dual-Port Static RAM Features • True dual-ported memory cells which allow simultaneous access of the same memory location • Six Flow-Through/Pipelined devices — 32K x 8/9 organizations CY7C09079A/179A


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    CY7C09079A/89/99 CY7C09179A/89/99 32K/64K/128K CY7C09079A/179A) CY7C09089/189) CY7C09099/199) IDT709079 IDT709089 PDF

    IDT709279

    Contextual Info: 25/0251 CY7C09279/89 CY7C09379/89 32K/64K x16/18 Synchronous Dual Port Static RAM Features • True dual-ported memory cells which allow simultaneous access of the same memory location • Six Flow-Through/Pipelined devices — 32K x 16/18 organization CY7C09279/379


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    CY7C09279/89 CY7C09379/89 32K/64K x16/18 CY7C09279/379) CY7C09289/389) 100MHz 35-micron IDT709279 PDF

    IDT709079

    Abstract: IDT709089
    Contextual Info: 025/0251 CY7C09079/89/99 CY7C09179/89/99 PRELIMINARY 32K/64K/128K x 8/9 Synchronous Dual-Port Static RAM Features • True Dual-Ported memory cells which allow simultaneous access of the same memory location • 6 Flow-Through/Pipelined devices — 32K x 8/9 organizations CY7C09079/179


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    CY7C09079/89/99 CY7C09179/89/99 32K/64K/128K CY7C09079/179) CY7C09089/189) CY7C09099/199) IDT709079 IDT709089 PDF

    IDT709089

    Abstract: tdc 410
    Contextual Info: 25/0251 CY7C09089/99 CY7C09189/99 64K/128K x 8/9 Synchronous Dual-Port Static RAM Features • True dual-ported memory cells which allow simultaneous access of the same memory location • Six Flow-Through/Pipelined devices — 64K x 8/9 organizations CY7C09089/189


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    CY7C09089/99 CY7C09189/99 64K/128K CY7C09089/189) CY7C09099/199) 100MHz 35-micron CY7C09089/99, IDT709089 tdc 410 PDF

    IDT709079

    Abstract: IDT709089
    Contextual Info: fax id: 5216 51 CY7C09079/89/99 CY7C09179/89/99 PRELIMINARY 32K/64K/128K x 8/9 Synchronous Dual Port Static RAM Features • True Dual-Ported memory cells which allow simultaneous access of the same memory location • 6 Flow-Through/Pipelined devices — 32K x 8/9 organizations CY7C09079/179


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    CY7C09079/89/99 CY7C09179/89/99 32K/64K/128K CY7C09079/179) CY7C09089/189) CY7C09099/199) IDT709079 IDT709089 PDF

    A12L

    Abstract: A13L CY7C09159 CY7C09169
    Contextual Info: 1 CY7C09159 CY7C09169 PRELIMINARY 8K/16K x 9 Synchronous Dual-Port Static RAM Features • True dual-ported memory cells which allow simultaneous access of the same memory location • Two Flow-Through/Pipelined devices — 8K x 9 organization CY7C09159


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    CY7C09159 CY7C09169 8K/16K CY7C09159) CY7C09169) 100-MHz 35-micron A12L A13L CY7C09159 CY7C09169 PDF

    A12L

    Abstract: CY7C09349 CY7C09359 fae 347
    Contextual Info: 1 CY7C09349 CY7C09359 PRELIMINARY 4K/8K x 18 Synchronous Dual-Port Static RAM Features • True dual-ported memory cells which allow simultaneous access of the same memory location • Two Flow-Through/Pipelined devices — 4K x 18 organization CY7C09349


    Original
    CY7C09349 CY7C09359 CY7C09349) CY7C09359) 100-MHz 35-micron A12L CY7C09349 CY7C09359 fae 347 PDF

    IDT709089

    Contextual Info: 1 CY7C09089/99 CY7C09189/99 64K/128K x 8/9 Synchronous Dual-Port Static RAM Features • True dual-ported memory cells which allow simultaneous access of the same memory location • Six Flow-Through/Pipelined devices — 64K x 8/9 organizations CY7C09089/189


    Original
    CY7C09089/99 CY7C09189/99 64K/128K CY7C09089/189) CY7C09099/199) 100MHz 35-micron IDT709089 PDF

    UBL 025

    Abstract: IDT709269 IDT709279 CY7C09269-12AI CY7C09279-12AI
    Contextual Info: 025/0251 CY7C09269/79/89 CY7C09369/79/89 PRELIMINARY 16K/32K/64K x16/18 Synchronous Dual Port Static RAM Features • True Dual-Ported memory cells which allow simultaneous access of the same memory location • 6 Flow-Through/Pipelined devices — 16K x 16/18 organization CY7C09269/369


    Original
    CY7C09269/79/89 CY7C09369/79/89 16K/32K/64K x16/18 CY7C09269/369) CY7C09279/379) CY7C09289/389) 100-MHz UBL 025 IDT709269 IDT709279 CY7C09269-12AI CY7C09279-12AI PDF

    z0800206

    Abstract: Z0800106 Z0800110 Z08002 Z0800 Z0800204CMB zilog z8001 1065D Z08002-06CMB TDA 2025
    Contextual Info: ZIL06 INC 17E D • ^ 3 4 0 4 3 0013b77 T Z8001 / Z 80023 Military Z8000® CPU Central Processing Unit 17 '! - ^ Military Electrical Specification o -7 September 1988 FEATURES ■ Regular, easy-to-use architecture ■ Instruction set more powerful than many minicomputers


    OCR Scan
    ZIL06 0013b77 Z8001® Z8000® 32-bit Z8010TM Z8002 40-pin 44-pln z0800206 Z0800106 Z0800110 Z08002 Z0800 Z0800204CMB zilog z8001 1065D Z08002-06CMB TDA 2025 PDF

    nonseg

    Contextual Info: Z8001 / Z8002® Military Z8000® CPU Central Processing Unit Military Electrical Specification 17 :1 M llO y September 1988 FEATURES • Regular, easy-to-use architecture ■ Instruction set more powerful than many minicomputers ■ Directly addresses 8


    OCR Scan
    Z8001Â Z8002Â Z8000Â 32-bit Z8010â nonseg PDF

    Z8002A

    Abstract: scr LDK packages
    Contextual Info: Z8001VZ8002* 16-Bit Microprocessors 2008Z/.L008Z DISTINCTIVE CHARACTERISTICS • • • 4, 6, 8 MHz CPU Clock High throughput with low system clock rate tor easi­ er system design Powerful General Register Architecture 16 general registers provide high throughput in all


    OCR Scan
    Z8001VZ8002* 16-Bit 2008Z/ L008Z 32-bit 40-pin Z8002 Z8001 /Z8002 Z8002A scr LDK packages PDF

    ba6l

    Abstract: 70V7339 A12L IDT70V7339 IDT70V7339S
    Contextual Info: Š HIGH-SPEED 3.3V 512K x 18 SYNCHRONOUS BANK-SWITCHABLE DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE IDT70V7339S Features: ◆ ◆ ◆ ◆ ◆ ◆ ◆ 512K x 18 Synchronous Bank-Switchable Dual-ported SRAM Architecture – 64 independent 8K x 18 banks


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    IDT70V7339S 200MHz 166MHz 133MHz) 14Gbps BC-256 144-pin ba6l 70V7339 A12L IDT70V7339 IDT70V7339S PDF

    tdc 310

    Abstract: Z80A Z80L
    Contextual Info: Z 8340 Low Power Z80 L SIO Serial Input/Output AC and DC Characteristics March 1985 ABSOLUTE MAXIMUM RATINGS Stresses greater than those listed under Absolute M axim um Ratings may cause perm anent d a m ag e to th e device. This is a stress rating only;


    OCR Scan
    Z8340 40-pin Z8340-1 Z8340-3 tdc 310 Z80A Z80L PDF

    Contextual Info: ZILOG INC 72 DE| 4 t m 3 QQG5M05 fi | T-75-37-07 Z 8340 Low Power Z80 L SIO Serial Input/Output AC and DC Characteristics March 1985 ABSOLUTE MAXIMUM RATINGS Voltages on all pins with respect t o G N D . - 0 . 3 V to + 7.0V


    OCR Scan
    QQG5M05 T-75-37-07 0D0S40t, 40-pln Z8340-1 PDF