TABLE OF EQUIVALENT TTL-IC VALUES Search Results

Contextual Info: SONY CXB1581Q Fibre Channel Transmitter Description The CXB1581Q is a transmitter IC with a built-in PLL for high-speed serial data transmission. It can be used together with the receiver IC, CXB1582Q, as a chip set; and 1062.5Mbaud, 20-bit or 531.25Mbaud, 10-bit opera­

Contextual Info: SONY CXB1582Q Fibre Channel Receiver Description The CXB1582Q is a receiver IC with a built-in PLL clock recovery circuit for high-speed serial data reception. It can be used together with the transmitter IC CXB1581Q as a chip set, and 1062.5Mbaud, 20bit or 531.25Mbaud, 10-bit operation can be selected.

Contextual Info: SONY CXB1590Q SDH 8 bit 622 Mbps Transceiver Description The CXB1590Q is a transceiver IC with built-in PLL for ATM network. For a receiver 622 Mbps serial data is received and output it as the 8-bit parallel data; for a transmitter 622 Mbps 8-bit parallel data is

CY74FCT16244T

Contextual Info: fax id: 7254 FCT is Low Power Power Characteristics of FCT From Cypress Introduction This application note presents and analyzes the power dissipation characteristics of FCT logic products manufactured by Cypress Semiconductor. No Direct Current DC FCT logic from Cypress uses P-channel pull-up and N-channel pull-down MOS transistors. Ideally, there is no direct current path between VCC and ground, so there are no quiescent

Contextual Info: CXB1582Q SONY Fibre Channel Receiver Description The CXB1582Q is a receiver IC with a built-in PLL clock recovery circuit for high-speed serial data recep­ tion. It can be used together with the transmitter IC, CXB1581Q, as a chip set and 1062.5Mbaud, 20-bit or

CXB1595AN

Abstract: 0.022uf
Contextual Info: CXB1595AN Fibre Channel Repeater Description The CXB1595AN is a clock and data recovery IC for fibre channel 1.0625Gbaud with a built-in PLL. This IC incorporates a port bypass circuit and is suitable for disk array and FC-AL HUB, etc. Features • Conforms to ANSI X3T11 Fibre Channel standard

AN-154

Abstract: SSOP-56 810-t 388915T CERPACK equivalent
Contextual Info: ESTIMATING POWER DISSIPATION IN CMOS DEVICES APPLICATION NOTE AN-154 Integrated Device Technology, Inc. By Anupama Hegde TJMAX. TJMAX is normally based on the limits imposed by die Due to higher system frequencies, new packages and reliability. Based on this TJMAX limit, maximum allowable

Contextual Info: gr oup Data Sheet January 1999 Lucent Technologies Bell Labs Innovations 1340-Type Lightwave Receiver Operation at 1.3 |am or 1.55 |am wavelengths Operating case temperature range of -4 0 °C to +85 °C Applications • Telecommunications — Inter- and intraoffice SONET/ITU-T SDH

qml-38535

Abstract: CQCC1-N20 GDFP2-F20
Contextual Info: REVISIONS DATE YR-MO-DA APPROVED Correct VCC and VIH values for ground bounce noise tests. - cfs 97- 04-24 Monica L. Poelking Change the device name to reflect the Bus Hold feature, and adjust limits to characterize the performance of the optimized die. Editorial changes

VIPER IC

Abstract: viper 17 L viper gate control circuits OAI221 VIPer Design Software internal structure of ic 741 on222 transistor ic 741 comparator signal generator OA4444 VIPER
Contextual Info: SEMICONDUCTOR CORPORATION Data Sheet Hjgh Performance¡ Low Cosí Viper Family Viper Family Gate Arrays Features • 7,000-13,000 Usable Gates, Channelless Array Architecture • Industry Standard Plastic Packaging • Superior Speed/Power Performance and Cost

LC6000

Abstract: LSI CMOS GATE ARRAY IC 7400 NAND Signal Path Designer IC TTL 7400 quiescent power
Contextual Info: L S I LOGIC CÓRP TO LOGIC D E | S304ÖD4 OODDTQE S |~_ ^ 9 0 ^ 0 0 9 0 2 D LSI Logic Corporation 1551 McCarthy Blvd Milpitas CA 95035 408.433.8000 Telex 172153 LMb6000 Micro bASIC Arrays Prelim inary Description The LMbGOOO Micro bASIC Channel-Free™ HCMOS

4-bit full adder using nand gates and 3*8 decoder

Abstract: gec plessey ula df69 DF Series DF-Series 1.8 GHz direct frequency vco with cad assessment df83 30DF1 T3265 filter for GPS spice
Contextual Info: S i GEC PLESSEY S E M I C O N D U C T O R S DS2312-3-1 ULA DF SERIES HIGH PERFORMANCE MIXED DIGITAL/ANALOG ARRAY FAMILY S u p e rs e d e s J u n e 1990 ed itio n The D F series of arrays is designed to provide cost effective single chip solutions to high speed combined digital and analog

TLY 2741

Abstract: SMd 6CA MQUAD 100175 Logic Package Information 100175 package 100175 smd Package Information 100175 translator Logic Package Information 100175 translator Logic smd Package Information TQ9303 TQ9501
Contextual Info: S E M I C O N D U C T O R , I N C 71 TQ9501/9502 531/1063 Mbaud Fibre Channel Transmitter and Receiver part of the FC531/FC1063 Fibre Channel 531 and 1063 Megabaud chip set.In addition to the transmitter and receiver, TriQuint offers the ENcoder/ DATACO M

ALU IC 74181

Abstract: ALU IC 74181 FUNCTION TABLE IC 74181 BTS18 ALU IC 74181 circuit IC 74181 alu 8 bit barrel shifter 7400 fan-out IC 7400 truth table IC 7400 nand gate
Contextual Info: 7- c o r p o r a t io n c . _ Silicon-Gate L L 5 0 0 0 S e r ie s Loaic Arrays O u ^ •J00941 C -S L- r , General The LL5000 series of silicon-gate HCMOS logic arrays from LSI LOGIC CORPORATION exhibits bipolar speeds, while at the same time, offers low power

64 PIN CERDIP

Contextual Info: HONEYWELL DIGITAL PRODUCT bb D E * 4SS14S3 0000050 b • ■ ■ RAD HARD ECL/TTL GATE ARRAY PRODUCT DESCRIPTION The HM1000R Gate Array Figure 1 is an 800 pico­ second, 1000 equivalent gate density LSI monolithic integrated circuit built using Honeywell’s radiation

Contextual Info: S E M IC O N D U C T O R w w w .fairchildsem i.com tm TDC1 01 6 Video Speed D/A Converter 1 0 - B i t , 20 Msps Features Description • • • • • • • • The TDC1016 is a bipolar monolithic digital-to-analog converter which can convert digital data into an analog volt­

Contextual Info: fax id: 5000 «f C Y 101E383 c y pr es s ECL/TTL/ECL Translator and High-Speed Bus Driver Features • BiCMOS for optimum speed/power • High speed max. — 3.0 ns tpD TTL-to-ECL — 4 ns tpD ECL-to-TTL Low skew < ± 1 ns Can operate on single +5V supply

AC/ACT CMOS family characteristics

Abstract: AN6525 Difference between LS, HC, HCT devices 74 Series IC Manual plotter AN-6525 HARRIS PACKAGE LOGIC FCT scr 2 22m four-layer diode act240 harris
Contextual Info: Technical Overview Features AC/ACT Family Features The Harris AC/ACT series of Advanced High Speed CMOS Integrated Circuits is comprised of a broad range of logic types equivalent in performance and speed to FAST, AS Advanced Schottky , and S (Schottky) bipolar types, but

HCL ME 1014

Contextual Info: Æ 9c t e ! P re lim in a ry RadTolerant RAD-PAK Field Programmable Gate Arrays F e a tu re s R a d ia tio n C h a r a c te r is t ic s • RAD-PAK® Package Technology from Space Electronics, Inc. • Improved Total Ionizing Dose TID Survivability - Can Improve TID 2-10x Over Standard Package

Contextual Info: CY101E383 ECL/TTL/ECL Translator and High-Speed Bus Driver ’# C Y P R E S S Features Functional Description • B iC M O S for optimum speed/power The C Y IO IL3 K 3 is a ncw-gcneriition T T L- to - LC L and I-CL-to-ITL logic level Iranslalor designed tor high-performance

CY101E383

Abstract: diode SKE 39
Contextual Info: W r CY10E383 CY101E383 CYPRESS ECL/TTL/ECL Translator and High-Speed Bus Driver Features Functional Description • B iC M O S for optim um speed/power • H igh speed max. — 2.5 n s Ipu TTL-to-EC L — 3.5 n s tpo EC L-to-TTL The CY10/101E383 is a new-generation

CY101E383

Abstract: E383 E1472
Contextual Info: fax id: 5000 i , *" : :V:V:V:V:V:g:-v- : : ^ :^ ; ^3»* i ; : M m : M : i : m : CY101E383 ECL/TTL/ECL Translator and High-Speed Bus Driver Features • BiCMOS for optimum speed/power • High speed max. — 3.0 ns tpQ TTL-to-ECL — 4 ns tpQ ECL-to-TTL

CXB1595AN

Contextual Info: SONY CXB1595AN Fibre Channel Repeater Description The CXB1595AN is a clock and data recovery IC for fibre channel 1.0625Gbaud with a built-in PLL. This IC incorporates a port bypass circuit and is suitable for disk array and FC-AL HUB, etc. Features • Conforms to ANSI X3T11 Fibre Channel standard

ALU IC 74181 circuit diagram

Abstract: TTL 74189
Contextual Info: ]>î| G5S7S5b DOEIOOB 1 ADV MICRO P LA /P LE/A RR AY S 7h 0 2 5 7 5 2 6 ADV MICRO PLA/PLE/ARRAYS 76C 21003 T-42-11-09 A m 7 2 2 a Q 2200 Gate HCMOS Evaluation Macrocell Array & ¡ it PRELIMINARY > 3 •Vj DISTINCTIVE CHARACTERISTICS Delay measurement block: