T7777 Search Results

cable groups

Abstract: 1-1490-10 1148-3
Contextual Info: KINGS 1 - 1 4 8 3 - 1 0 a n d 1 - 8 1 1 4 - 1 0 F le x ib o o ts These strain-relief Flexiboots protect the cable from wear, fatigue and weather. See chart below for available cables 1.75 (44.4) - 1.50 (38.1) - - / / / / / / /////T77777? .44 (11.2) D.

square d 9003

Abstract: 725-L1
Contextual Info: 4 THIS DRAWING IS UNPUBLISHED. COPYRIGHT 3 RELEASED FOR PUBLICATION ALL RIGHTS RESERVED. BY TYCO ELECTRONICS CORPORATION. D CL ro < CN -0.48+0.08 [.01 9±.003] 1-3.1 8+0.05 [.1 25+.002] i—2.46 ±0.1 5 [.097+.006] 6.22 [-2 4 5 ] 9.02 [.3 55] 2 .54 [. 1 OO]

2SC4116GR

Abstract: ADS varactor diode 15 K26 011110 drivers 5k21 KRY 112 46 KRY 112 75/1 TC9318FA tc9318 4bit counter KRY 112 75
Contextual Info: TOSHIBA TC9318FA/FB TOSHIBA CMOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC TC9318FA, TC9318FB SINGLE CHIP DTS MICROCONTROLLER DTS-21 The TC9318FA and TC9318FB are a 4bit CMOS microcontroller for signal chip digital tuning systems. It is capable of functioning at a low voltage of 3V and

Contextual Info: CMOS 524,288 x 8 bit Fast Page Mode Dynamic RAM • DESCRIPTION The Fujitsu MB81V4800S is a fully decoded CMOS Dynamic RAM DRA:M|i:that contains 4,194,304 memory cells accessible in 8-bit increments. The MB81V4800S features a “fast page” made of operation whereby high­

BI71

Contextual Info: HM5283206 Series 131,072-word x 32-bit x 2-bank Synchronous Graphic RAM HITACHI ADE-203-223A Z Rev. 1.0 May. 30, 1996 Description All inputs and outputs signals refers to the rising edge of the clock input. The HM5283206 provides 2 banks to realize better performance. 8 column block write function and write per bit function are provided for

Contextual Info: THIS COPY IS PROVIDED ON A RESTRICTED BASIS AND IS NOT TO BE USED IN ANY W AY DETRIMENTAL TO THE INTERESTS OF PANDUIT CORP. M aterial High C on du ctivity Seamless C o p p e r Tube Plating Electro-Tin Wire Size 1/0 AWG Wire Type Stranded C opper; Class B:

CL-21 capacitor

Abstract: z5u .05 PA 4013 cl31f1 K20xC
Contextual Info: SURGE Components, Inc. 1016 Grand Boulevard Deer Park, NY 11729 • 631595-1818 • FAX: 631 595-1283 SCM Series MULTILAYER CERAMIC CHIP CAPACITOR FEATURES: □ Miniature Size □ W ide Capacitance, T C and Voltage Range □ Highly Reliable Performance □ Industry Standard Size

Contextual Info: MOS INTEGRATED CIRCUIT ¿¿PD4 2 S 1 6 1 6 5 L , 4 2 1 6 1 6 5 L 3.3 V OPERATION 16 M-BIT DYNAMIC RAM 1 M-WORD BY 16-BIT, HYPER PAGE MODE, BYTE READ/WRITE MODE D escription The ì ì PD42S16165L, 4216165Lare 1 048 576 w ords by 16 bits dynamic CMOS RAMs w ith optional hyper page

we32100

Contextual Info: WE 32106 Math Acceleration Unit Description The WE 32106 Math Acceleration Unit MAU provides floating-point capability for the WE 32100 Microprocessor and is fully compatible with the IEEE Standard for Binary FloatingPoint Arithmetic (ANSI/IEEE Std. 754-1985). It

256KX4

Abstract: V53C104B V53C104 casco battery
Contextual Info: JVH VITEUC V53C104B HIGH PERFORMANCE, LO W POW ER 256K X 4 B IT FA S T PAGE MODE CMOS DYNAMIC RAM PRELIMINARY 60/60L 70/70L 80/80L Max. RAS Access Time, tp ^ 60 ns 70 ns 80 ns Max. Column Address Access Time, (tCAA) 30 ns 35 ns 40 ns Min. Fast Page Mode Cyde Time, (tp^)

P3420

Abstract: DASL
Contextual Info: In developing the architecture of this IS D N chip set, Nation­ al's major objective has been to create a flexible set of building blocks which provide elegant and cost-effective so ­ lutions for a wide range of applications. With just a few high­ ly integrated devices, a broad spectrum of IS D N equipment

Contextual Info: MOSEL- VITELIC V52C4256 MULTIPORT VIDEO RAM WITH 256K X 4 DRAM AND 5 1 2 X 4 SAM HIGH PERFORMANCE V52C4256 60 PRELIMINARY 80 10 70 ns 80 ns 100 ns 20 ns 25 ns 25 ns 40 ns 50 ns 70 Max. RAS Access Time, tp^c 60 ns Max. CAS Access Time, <tQAC) 15 ns Max. Column Address Access Time, (tAA)

V52C8128

Abstract: V52C8128-80
Contextual Info: MOSEL- VITELIC V52C8128 MULTIPORT VIDEO RAM WITH 128K X 8 DRAM AND 256 X 8 SAM HIGH PERFORMANCE V52C8128 70 PRELIMINARY 80 10 Max. RAS Access Time, tRAc 70 ns 80 ns 100 ns Max. CAS Access Time, (tcAc) 20 ns 25 ns 25 ns Max. Column Address Access Time, ( t ^ )

Contextual Info: •HANDLING PRECAUTIONS Soldering iron Types Lamps/flat packages Temperature at tip of iron: Pre-heating: lOO’C max. R esin surface tem perature (30 W max.i 60 sec, max. Bath temperature: 260‘ C max. Location - A! least 3 mm away from resin body Reflow soldering

Contextual Info: MOSEL MS64100 32K x 8 High Speed CMOS Static RAM with Parity Generator and Checker FEATURES DESCRIPTION • Organization: 32768 words x 8 bits The MOSEL MS64100 Parity RAM is a high speed, CMOS Static RAM with internal parity generation and parity error detection circuitry. It is organized externally as 32,768

Contextual Info: M O S EL V IT E L IC V53C8129H ULTRA-HIGH PERFORMANCE, 128K X 8 BIT EDO PAGE MODE CMOS DYNAMIC RAM PRELIMINARY 35 40 45 50 Max. RAS Access Time, tRAC 35 ns 40 ns 45 ns 50 ns Max. Column Address Access Time, (Icu ò 18 ns 20 ns 22 ns 24 ns Min. Fast Page Mode With EDO Cycle Time, (tpC)

rca thyristor manual

Abstract: HN623258 101490
Contextual Info: Quick Reference Guide to Hitachi 1C Memories Package Information Reliability of Hitachi 1C Memories Applications MOS Static RAM MOS Pseudo Static RAM Application Specific Memory MOS Dynamic RAM MOS Dynamic RAM Module MOS Mask ROM MOS PROM ECL RAM P> Jc^< j

R40 AH

Contextual Info: HM5283206 Series 131,072-word x 32-bit x 2-bank Synchronous Graphic RAM HITACHI ADE-203-223A Z Rev. 1.0 May. 30, 1996 Description All inputs and outputs signals refers to the rising edge of the clock input. The HM5283206 provides 2 banks to realize better performance. 8 column block write function and write per bit function are

424400LA-70

Contextual Info: NEC MOS INTEGRATED CIRCUIT ¿¿PD42S4400L, 424400L 3.3 V OPERATION 4 M-BIT DYNAMIC RAM 1 M-WORD BY 4-BIT, FAST PAGE MODE Description The /xPD42S4400L, 424400L are 1 048 576 words by 4 bits dynamic C M O S RAMs. The fast page mode capability realize high speed access and low power consumption.

UPD4265160-A60

Contextual Info: DATA SHEET NEC MOS INTEGRATED CIRCUIT juPD4264160, 4265160 6 4 M -B IT D YN A M IC RAM 4 M -W O R D BY 16-BIT, FAST PAGE M O DE Description The /iPD 4264160,4265160 are 4,194,304 words by 16 bits CMOS dynamic RAMs. The fast page mode capability realize high speed access and low power consumption.

PD4264800

Contextual Info: PRELIMINARY DATA SHEET NEC / MOS INTEGRATED CIRCUIT / ¿¿PD4264800, 4265800 64M -B IT DYNAMIC RAM 8 M-WORD BY 8-BIT, FAST PAGE MODE D e s c rip tio n The iiPD 4264800, 4265800 are 8,388,608 w ords by 8 bits dynam ic CMOS RAMs. The fast page mode capability

hilti te 24

Abstract: hilti te 17 GO 440 104 esm 433 rac
Contextual Info: DATA SHEET NEC MOS INTEGRATED CIRCUIT ¿¿P D 42S18165L , 4 2 1 8 1 6 5 L 3.3 V OPERATION 16 M-BIT DYNAMIC RAM 1 M-WORD BY 16-BIT, EDO, BYTE READ/WRITE MODE Description The .¿/PD42S18165L, 4218165L are 1,048,576 words by 16 bits CMOS dynamic RAMs with optional EOO

00000-1FFFF

Abstract: Y-1002 XM23 y1013 MSM6792GS-BK 20000-3FFFF 40000-5FFFF C0000-DFFFF Y1012
Contextual Info: O K I Semiconductor M S M 6 7 9 2 SRAM Interface 1C GENERAL DESCRIPTIO N When connected to OKI’s recording and playback IC, the MSM6792 allows the use of SRAM Static-RAM , EPROM or mask ROM as a voice data storage memory. This device hasa built-in internal address generation circuit. External single clock input enables

Contextual Info: Temperature Controller • £ . . . . . ' ■ 1 , ‘""^ . “ ' j, ', * .i.1 / ■ -i"*'. ' ‘\ ‘i ‘‘?r'.v£?.,y . ■* User's Manual Cat. No. H101-E1-1 Preface The E5GN compact temperature controller features the following: • The E5GN can be mounted on compact panels