T74LS113A Search Results

T74LS

Contextual Info: SCS-THOMSON [iJ g ïïl P u S T 7 4 L S 1 13 A DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP DESCRIPTION The T74LS113A offers individual J, K, set and clock inputs. These monolithic dual flip-flops are designed so that when the clock goes HIGH, the inputs are

Contextual Info: ss DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP $0^ DESCRIPTION The T54LS/T74LS113/113A offers individual J, K, set and clock inputs. These monolithic dual flipflops are designed so that when the clock goes HIGH, the inputs are enabled and data will be ac­ cepted. The logic level of the J and K may be allo­

T74LS244

Abstract: T74LS5 t74LS161a sgs T74LS293 T74LS02
Contextual Info: ALPHANUMERICAL INDEX I Type Number T74LS00 T74LS01 T74LS02 T74LS03 T74LS04 T74LS05 T74LS08 T74LS09 T74LS10 T74LS11 T74LS12 T74LS13 T74LS14 T74LS15 T74LS20 T74LS21 T74LS22 T74LS26 T74LS27 T74LS28 T74LS30 T74LS32 T74LS33 T74LS37 T74LS38 T74LS40 T74LS42 T74LS51

Contextual Info: s G 0 ?E S -T H O n S O N D | 7 ^ 5 ^ 3 7 D 01b 033 3 | LOW POWER SCHOTTKY i T54LSÌ13/113^ T74LS113/113A INTEGRATED CIRCUITS 67C 1 6 1 6 1 D T -*& -o 7 -o 7 DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP DESCRIPTIO N The T54LS/T74LS113 /1 13A offers individual J, K,

LC-D023

Contextual Info: DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP DESCRIPTION The T54LS/T74LS113/113A offers individual J, K, set and clock inputs. These monolithic dual flip­ flops are designed so that when the clock goes HIGH, the inputs are enabled and data will be ac­ cepted. The logic level of the J and K may be allo­