T11B Search Results

E208

Abstract: T11B
Contextual Info: Device Orientation Vishay Siliconix Device Orientation PolarPAKr DEVICE ORIENTATION Package Method PolarPAK T1 E208 SSAA D T11B E208 SSAA D T11B E208 SSAA D T11B E208 SSAA D T11B User Direction of Feed Revision control of this drawing is maintained through Document Control, Pack Specification—PACK-0007-21

Asus MONITOR MOTHERBOARD CIRCUIT MANUAL

Abstract: T2D 83 diode gp026 st GP025 82430TX 82371EB Asus PC MOTHERBOARD CIRCUIT schematic diode T75A Asus PC MOTHERBOARD CIRCUIT MANUAL 8272A floppy disk controller block diagram
Contextual Info: PRELIMINARY DRAFT Intel Extended Temperature 82371EB PCI-TO-ISA/IDE Xcelerator PIIX4E Datasheet  Integrated 16 x 32-bit Buffer for IDE PCI Burst Transfers  Supports Glue-less “Swap-Bay” Option with Full Electrical Isolation Supported Kits for both Pentium and

Contextual Info: A B W A N O B O N IP O R Q W O Q N in te i 82091AA ADVANCED INTEGRATED PERIPHERAL AIP • Single-Chip PC Compatible I/O Solution for Notebook and Desktop Platforms: — 82078 Floppy Disk Controller Core — Two 16550 Compatible UARTs — One Multi-Function Parallel Port

82430LX

Contextual Info: in te * 82433LX/82433NX LOCAL BUS ACCELERATOR LBX Supports th e Full 64-bit Pentium- Processor Data Bus at Frequencies up to 66 MHz (82433LX and 82433NX) Dual-Port Architecture Allows Concurrent Operations on the Host and PCI Buses Drives 3.3V Signal Levels on the CPU

Contextual Info: intJ. 82375EB PCI-EISA Bridge PCEB Provides the Bridge Between the PCI Bus and EISA Bus 32-Bit Data Paths 100% PCI and EISA Compatible — PCI and EISA Master/Slave Interface — Directly Drives 10 PCI Loads and 8 EISA Slots — Supports PCI at 25 MHz to 33 MHz

82378ib

Contextual Info: A P M Ä M ! DM iP© I^[ìfflA'irD@ N] in te i 82378IB SYSTEM I/O SIO Provides the Bridge Between the PCI Bus and ISA Bus Arbitration for PCI Devices — Four PCI Masters are Supported — Fixed, Rotating, or a Combination of the Two 100% PCI and ISA Compatible

T32A scr

Abstract: t17c floppy controller pinout Intel 82072 intel floppy disk controller 8272 82091AA T16E 82077AA 82077SL SA10
Contextual Info: 82091AA ADVANCED INTEGRATED PERIPHERAL AIP Y Single-Chip PC Compatible I O Solution for Notebook and Desktop Platforms 82078 Floppy Disk Controller Core Two 16550 Compatible UARTs One Multi-Function Parallel Port IDE Interface Integrated Back Power Protection

100BASE-FX

Abstract: LS14 LXT970 LXT981 iriso intel 2732 eprom
Contextual Info: DATA SHEET DECEMBER, 1998 Revision 1.1 LXT981 Single-Speed, 5-Port Fast Ethernet Repeater with Integrated Management Support General Description Features The LXT981 is a 5-port Class II Fast Ethernet Repeater that is fully compliant with IEEE 802.3 standards. Four ports

T3D 34 diode

Abstract: 82440LX Diode T3D 57 t57b T27b t59b T31C Transistor t59c ISA BUS spec t119
Contextual Info: E DATASHEET ADDENDUM 82371AB PIIX4 PCI ISA IDE Xcelerator Timing Specifications September 1997 Order Number: 290548-001 Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms and Conditions

SDC40

Contextual Info: WESTERN DIGITAL CORP =1710220 0001=205 T SIE D Advance Information EE6030 Cache/DRAM and Channel Control Device Complete compatibility with the IBM* Personal System/2* Models 70 and 80 Direct-Mapped Cache Controller Includes the following: Page Mode DRAM Controller

mobile MOTHERBOARD CIRCUIT diagram

Abstract: 8080 intel databook 221-291 8080 intel microprocessor pin diagram INTEL DX2 intel L2 cache burst length 241428 D6378
Contextual Info: MOBILE PENTIUM PROCESSOR WITH MMX TECHNOLOGY ON 0.25 MICRON Operating Frequency 166 MHz 200 MHz n Support for MMX™ Technology n Compatible with Large Software Base  MS-DOS*, Windows*, OS/2*, UNIX* n 32-Bit CPU with 64-Bit Data Bus n Superscalar Architecture

T120 crystal

Abstract: T55B C1995 DP83910A DP8392 DP83932C-20 T69A
Contextual Info: DP83932C-20 25 33 MHz SONIC TM Systems-Oriented Network Interface Controller General Description The SONIC Systems-Oriented Network Interface Controller is a second-generation Ethernet Controller designed to meet the demands of today’s high-speed 32- and 16-bit systems Its system interface operates with a high speed DMA

diode T35 -4-D6

Abstract: A23 851 diode am24 "pin compatible" mobile MOTHERBOARD CIRCUIT diagram AK32 AM34 AN33 Desktop Board cce intel mmx
Contextual Info: E MOBILE PENTIUM PROCESSOR WITH MMX TECHNOLOGY Maximum Operating Frequency n n n n n n n 133 MHz n Support for MMX™ Technology Compatible with Large Software Base  MS-DOS*, Windows*, OS/2*, UNIX* 32-Bit CPU with 64-Bit Data Bus Superscalar Architecture

241561

Abstract: Intel 80386 programming model, memory paging 273206 273214 intel DOC Pentium MMX .25 MICRON 273232 Omega k type thermocouple range
Contextual Info: Extended Temperature Pentium Processor with MMX Technology Advance Information Datasheet Product Features • ■ ■ ■ ■ Support for MMX™ Technology Low-Power 0.25 Micron Process Technology — 1.8 V Core Supply for HLPBGA — 2.5 V I/O Interface

pentium MOTHERBOARD CIRCUIT diagram

Abstract: T40 N03 am24 "pin compatible" processor cross reference intel pentium MMX simd 1997 z02 surface mounted transistor
Contextual Info: Low-Power Embedded Pentium Processor with MMX Technology Datasheet Product Features • ■ ■ ■ ■ Support for MMX™ Technology Low-Power 0.25 Micron Process Technology — 1.9 V 166/266 MHz Core Supply for PPGA — 1.8 V (166 MHz) or 2.0 V (266 MHz)

SP126

Abstract: lg lcd tv panel circuit diagram free SPC8106F0B SPC8108FOC 4X12 lcd SP-1108 sp1 1r4 FL400 xe p001 XCSL
Contextual Info: S-MOS S Y S T E M S A Seiko Epson Affiliate SPC8106 LCD/CRT VGA CONTROLLER Data Sheet Copyright 1997 S-MOS Systems Inc. All rights reserved. VDC This document, and any text derived, extracted or transmitted from it, is the sole property of S-MOS Systems Inc. and may not be used, copied,

sonic g 700 a

Contextual Info: November 1995 DP83916 SONIC TM -16 Systems-Oriented Network Interface Controller General Description one for indicating status and control information and the other for fetching packet data The system can create a transmit queue allowing multiple packets to be transmitted

apic - s03

Abstract: 243292 80286 microprocessor pin .doc format AM34 Diode T3 D46 PP0115 intel pentium MMX simd 1997 SL Enhanced Mobile Pentium Processor with MMX Technology Voltage Reduction Power Supply Design Considerations a
Contextual Info: MOBILE PENTIUM PROCESSOR WITH MMX TECHNOLOGY Maximum Operating Frequency iCOMP ® Index 2.0 Rating 150 MHz 166 MHz 144 160 Note: Contact Intel Corporation for more information about iCOMP ® Index 2.0 ratings. Support for MMX™ Technology Compatible with Large Software Base

3at2

Abstract: MN102 PANASONIC pic writer
Contextual Info: MICROCOMPUTER MN102H MN102H60G/60K/F60G/F60K LSI User’s Manual Pub.No.22360-013E PanaX Series is a trademark of Matsushita Electric Industrial Co., Ltd. The other corporation names, logotype and product names written in this book are trademarks or registered trademarks of their

aui isolation transformer

Abstract: bcm switching software NEC AMC network-interface buffer register source-address SAS controller chip TDA 150X 10BASE2 10BASE5 C1995 DP83910A
Contextual Info: DP83934CVUL-20 25 MHz SONIC TM -T Systems-Oriented Network Interface Controller with Twisted Pair Interface General Description The SONIC-T Systems-Oriented Network Interface Controller with Twisted Pair is a second-generation Ethernet Controller designed to meet the demands of today’s high-speed

LTSX

Abstract: BF193 SC2000S
Contextual Info: Universal Timeslot Interchang r f lT i Data Sheet Preliminary Information November 1997 V L S I ^ Technology l i l l ^SSr K a 9 ie a 9 2 0 0 0 Universal lîmeslot Interchange T a b le o f C o n te n ts F e a t u r e s .

Micropower Buffered Variable Voltage

Abstract: PFBGA 160x240
Contextual Info: S1D13708 Embedded Memory LCD Controller S1D13708 TECHNICAL MANUAL Document Number: X39A-Q-001-01 Copyright 2001 Epson Research and Development, Inc. All Rights Reserved. Information in this document is subject to change without notice. You may download and use this document, but only for your own use in

440BX

Abstract: Diode T3D 57 t26b t2d t3d T3D 53 diode T3D 62 82443BX t2d 68 T13A T14A
Contextual Info: 82443BX Host Bridge/Controller Electrical and Thermal Specification Timing Specification Datasheet Addendum Product Features • ■ ■ Processor/host bus support —Optimized for Pentium II processor at 100 MHz system bus frequency; Support for 66 MHz

T55B

Abstract: T71A t19c t17c t61b t58b t57b T27b t65a T3D 62
Contextual Info: 82371AB PCI ISA IDE Xcelerator PIIX4 23.0 Clock, Reset, ISA Bus, X-Bus, and Host Timing Diagrams Figure 41. Clock Timing Period High Time PCICLK, SYSCLK, OSC 2.0V 0.8V Low Time Fall Time Rise Time Figure 42. Reset Inactive Timing SUS_STAT[1:2]# t2f PCIRST#, RSTDRV