SY100S350JCTR Search Results

F100K

Abstract: SY100S350 SY100S350FC SY100S350FCTR SY100S350JC
Contextual Info: Micrel, Inc. SY100S350 FEATURES • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ SY100S350 HEX D-LATCH DESCRIPTION The SY100S350 offers six high-speed D-Latches with both true and complement outputs, and is performance compatible for use with high-performance ECL systems.

Contextual Info: « SYNERGY HEX D-LATCH SY100S350 SEMICONDUCTOR FEATURES • Max. transparent propagation delay of 900ps ■ Min. Master Reset and Enable pulse widths of 100ps ■ Ie e min. of -98m A ■ Industry standard 100K ECL levels ■ Extended supply voltage option:

Contextual Info: SY100S350 Micrel, Inc. FEATURES • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ SY100S350 HEX D-LATCH DESCRIPTION The SY100S350 offers six high-speed D-Latches with both true and complement outputs, and is performance compatible for use with high-performance ECL systems.

F100K

Abstract: SY100S350 SY100S350JC SY100S350JCTR
Contextual Info: SY100S350 Micrel, Inc. FEATURES • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ SY100S350 HEX D-LATCH DESCRIPTION The SY100S350 offers six high-speed D-Latches with both true and complement outputs, and is performance compatible for use with high-performance ECL systems.

Contextual Info: * HEX D-LATCH SYNERGY SEMICONDUCTOR FEATURES DESCRIPTION Max. transparent propagation delay of 900ps Min. Master Reset and Enable pulse widths of 100ps Ie e SY100S350 min. of -98mA ESD protection of 2000V Industry standard 100K ECL levels Extended supply voltage option:

F100K

Abstract: SY100S350 SY100S350FC SY100S350JC SY100S350JCTR
Contextual Info: HEX D-LATCH FEATURES Q1 Q1 Q0 D0 Q0 VEES PIN CONFIGURATIONS D1 11 10 9 8 7 6 5 D2 Ea 12 13 14 15 16 17 Eb 18 D3 VEE BLOCK DIAGRAM VEES MR D1 D0 R D2 24 23 22 21 20 19 18 D1 2 3 17 16 D0 Q0 15 14 Q0 Q1 13 7 8 9 10 11 12 Q1 Q4 4 5 Q4 6 Top View Flatpack F24-1

hex latch

Abstract: F100K SY100S350 SY100S350FC SY100S350JC SY100S350JCTR
Contextual Info: SY100S350 FINAL HEX D-LATCH FEATURES Q1 Q1 Q0 D0 Q0 VEES PIN CONFIGURATIONS D1 11 10 9 8 7 6 5 D2 Ea 12 13 14 15 16 17 Eb 18 D3 VEE BLOCK DIAGRAM VEES MR D1 D0 R D2 24 23 22 21 20 19 18 D1 2 3 17 16 D0 Q0 15 14 Q0 Q1 13 7 8 9 10 11 12 Q1 Q4 4 5 Q4 6 Top View

DI 437 EB

Contextual Info: * HEX D-LATCH SYNERGY SY100S350 SEMICONDUCTOR FEATURES DESCRIPTION Max. transparent propagation delay of 900ps Min. Master Reset and Enable pulse widths of 100ps I e e min. o f-9 8m A Industry standard 100K ECL levels Extended supply voltage option: V ee = -4.2V to -5.5V

Contextual Info: * HEX D-LATCH SYNERGY SY100S350 SEMICONDUCTOR FEATURES DESCRIPTION Max. transparent propagation delay of 900ps Min. Master Reset and Enable pulse widths of 100ps Iee min. o f-98 m A Industry standard 100K ECL levels Extended supply voltage option: V ee = -4.2V to -5.5V