STMICROELECTRONICS Z 25 Search Results

STM32F107* device marking

Abstract: stm32f107 stm32f105* errata STM32F10* I2C STM32F105xx SMBus Specification V2.0 stm32f105 STM32F105V8 STM32F10* USB STMicroelectronics marking code date
Contextual Info: STM32F105xx and STM32F107xx Errata sheet STM32F105xx and STM32F107xx revision Z connectivity line device limitations Silicon identification This errata sheet applies to the revision Z of the STMicroelectronics STM32F105xx and STM32F107xx connectivity line products. This family features an ARM 32-bit Cortex -M3

STM32F1

Abstract: STM32F100X4 STM32F100 STM32F100C4 STM32F100rb stm32f100c8 STM32F100CB STM32F100xx STM32F100C STM32F10* I2C errata
Contextual Info: STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB errata sheet STM32F100xx low and medium-density value line device limitations Silicon identification This errata sheet applies to the revision Z of the STMicroelectronics low and mediumdensity STM32F100xB value line products.

WLCSP64

Abstract: STM32F103RC STM32F103xE STM32F103VC stm32f103ve errata STM32F10* I2C errata STM32F101RC STM32F101RD STM32F101VD STM32F101ZC
Contextual Info: STM32F101xC/D/E and STM32F103xC/D/E Errata sheet STM32F101xC/D/E and STM32F103xC/D/E revision Z high-density device limitations Silicon identification This errata sheet applies to the revision Z of the STMicroelectronics STM32F101xC/D/E access line and STM32F103xC/D/E performance line high-density products. These families

WLCSP64

Abstract: STM32F10* I2C errata STM32F101RC STM32F101vc STM32F103RC STM32F103VC STM32F103xE STM32F101XC stm32f103ve FSMC reference manual
Contextual Info: STM32F101xC/D/E and STM32F103xC/D/E Errata sheet STM32F101xC/D/E and STM32F103xC/D/E revision Z high-density device limitations Silicon identification This errata sheet applies to the revision Z of the STMicroelectronics STM32F101xC/D/E access line and STM32F103xC/D/E performance line high-density products. These families

stm32f103z

Abstract: STM32F103VC STMICROELECTRONICS TOP making STM32F101VD STM32F103RC stm32f103vd STM32F103Ve STM32F103xE STM32F101RC ARM Cortex core
Contextual Info: STM32F101xC/D/E and STM32F103xC/D/E Errata sheet STM32F101xC/D/E and STM32F103xC/D/E revision Z high-density device limitations Silicon identification This errata sheet applies to the revision Z of the STMicroelectronics STM32F101xC/D/E access line and STM32F103xC/D/E performance line high-density products. These families

ideas

Abstract: COSMIC
Contextual Info: ST7 MICROCONTROLLER TRAINING z 5 - ST7 SOFTWARE TOOLS ¾ 5.1 - STMicroelectronics ASSEMBLY TOOLCHAIN ¾ 5.2 - HIWARE C TOOLCHAIN ¾ 5.3 - COSMIC C TOOLCHAIN 1 FILE AND APPLICATION FLOWS WINDOWS EPB .s19 Dedicated Triggers Board .elf CVDWARF WINDOWS STVD7 .lkf

STM32F103xxx

Abstract: STM32F10xxB stm32f102r8 STM32F102RB STM32F10xxx STM32F10* I2C stm32f103xxx manual ic ir 2112 STM32F10* I2C errata STM32F102x
Contextual Info: STM32F10xx8 and STM32F10xxB Errata sheet STM32F101x8/B, STM32F102x8/B and STM32F103x8/B medium-density device limitations Silicon identification This errata sheet applies to the revisions B, Z and Y of the STMicroelectronics mediumdensity STM32F101xx access line and STM32F103xx performance line products, and to

STM32F10xxB

Abstract: Part Marking STMicroelectronics flash memory STM32F10* USB STM32F10* I2C errata USART3 STM32F103xxx ARM Cortex core Date Code Marking STMicroelectronics SMBus Specification V2.0 STMicroelectronics marking code date
Contextual Info: STM32F10xx8 and STM32F10xxB Errata sheet STM32F101x8/B, STM32F102x8/B and STM32F103x8/B medium-density device limitations Silicon identification This errata sheet applies to the revisions B, Z and Y of the STMicroelectronics mediumdensity STM32F101xx access line and STM32F103xx performance line products, and to

speed control of dc motor using fuzzy logic controller

Abstract: 74LS00 Speed Control Of DC Motor Using Fuzzy Logic ST52x301 motor speed control by using dsp motor speed fuzzy control by using dsp 8SIP100 74LS00 DATA fuzzy logic for speed control dc motor 7sip100
Contextual Info: DC Motor Speed and Position Fuzzy Control Fuzzy Logic B.U. STMicroelectronics Fuzzy Logic B.U. 02/29/00 1 DC Motor Std. Control vs Fuzzy Control FUZZY CONTROL TRADITIONAL CONTROL r +- K + B + 1/S X C - - A F NEG. ZERO POS. NEG. NM VS VVS ZERO L Z S POS.

STM32F103VC

Abstract: STM32F103RC STM32F103xE STM32F10* I2C errata 548-72 STM32F103ZD USART STM32F101RC STM32F101RD stm32f103ve errata
Contextual Info: STM32F101xC/D/E and STM32F103xC/D/E Errata sheet STM32F101xC/D/E and STM32F103xC/D/E high-density device limitations Silicon identification This errata sheet applies to the revisions Z and Y of the STMicroelectronics STM32F101xC/D/E access line and STM32F103xC/D/E performance line high-density

DIP-20

Abstract: M74HCT643 M74HCT643B1R M74HCT643M1R M74HCT643RM13TR M74HCT643TTR
Contextual Info: M74HCT643 OCTAL BUS TRANSCEIVER WITH 3 STATE OUTPUTS INVERTED/NON INVERTED • ■ ■ ■ ■ ■ HIGH SPEED: tPD = 13ns (TYP.) at VCC = 4.5V LOW POWER DISSIPATION: ICC = 4µA(MAX.) at TA=25°C COMPATIBLE WITH TTL OUTPUTS : VIH = 2V (MIN.) VIL = 0.8V (MAX)

DIP-20

Abstract: M74HCT640 M74HCT640B1R M74HCT640M1R M74HCT640RM13TR M74HCT640TTR
Contextual Info: M74HCT640 OCTAL BUS TRANSCEIVER WITH 3 STATE OUTPUTS INVERTED • ■ ■ ■ ■ ■ HIGH SPEED: tPD = 13ns (TYP.) at VCC = 4.5V LOW POWER DISSIPATION: ICC = 4µA(MAX.) at TA=25°C COMPATIBLE WITH TTL OUTPUTS : VIH = 2V (MIN.) VIL = 0.8V (MAX) SYMMETRICAL OUTPUT IMPEDANCE:

DIP-20

Abstract: M74HCT643 M74HCT643B1R M74HCT643M1R M74HCT643RM13TR M74HCT643TTR
Contextual Info: M74HCT643 OCTAL BUS TRANSCEIVER WITH 3 STATE OUTPUTS INVERTED/NON INVERTED • ■ ■ ■ ■ ■ HIGH SPEED: tPD = 13ns (TYP.) at VCC = 4.5V LOW POWER DISSIPATION: ICC = 4µA(MAX.) at TA=25°C COMPATIBLE WITH TTL OUTPUTS : VIH = 2V (MIN.) VIL = 0.8V (MAX)

74V1T03

Abstract: 74V1T03C 74V1T03S
Contextual Info: 74V1T03  SINGLE 2-INPUT OPEN DRAIN NAND GATE PRELIMINARY DATA • ■ ■ ■ ■ ■ HIGH SPEED: tPD = 7 ns TYP. at VCC = 5V LOW POWER DISSIPATION: ICC = 1 µA (MAX.) at TA = 25 oC COMPATIBLE WITH TTL OUTPUTS: VIH = 2V (MIN), VIL = 0.8V (MAX) POWER DOWN PROTECTION ON INPUTS

DIP-20

Abstract: M74HCT245 M74HCT245B1R M74HCT245M1R M74HCT245RM13TR M74HCT245TTR
Contextual Info: M74HCT245 OCTAL BUS TRANSCEIVER WITH 3 STATE OUTPUTS NON INVERTED • ■ ■ ■ ■ ■ HIGH SPEED: tPD = 13ns (TYP.) at VCC = 4.5V LOW POWER DISSIPATION: ICC = 4µA(MAX.) at TA=25°C COMPATIBLE WITH TTL OUTPUTS : VIH = 2V (MIN.) VIL = 0.8V (MAX) SYMMETRICAL OUTPUT IMPEDANCE:

Contextual Info: M74HCT640 OCTAL BUS TRANSCEIVER WITH 3 STATE OUTPUTS INVERTED • ■ ■ ■ ■ ■ HIGH SPEED: tPD = 13ns (TYP.) at VCC = 4.5V LOW POWER DISSIPATION: ICC = 4µA(MAX.) at TA=25°C COMPATIBLE WITH TTL OUTPUTS : VIH = 2V (MIN.) VIL = 0.8V (MAX) SYMMETRICAL OUTPUT IMPEDANCE:

M74HC03RM13TR

Abstract: M74HC03TTR TSSOP14 M74HC03 M74HC03B1R M74HC03M1R
Contextual Info: M74HC03 QUAD 2-INPUT OPEN DRAIN NAND GATE • ■ ■ ■ ■ ■ HIGH SPEED: tPD = 8ns TYP. at VCC = 6V LOW POWER DISSIPATION: ICC = 1µA(MAX.) at TA=25°C HIGH NOISE IMMUNITY: VNIH = V NIL = 28 % VCC (MIN.) BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL WIDE OPERATING VOLTAGE RANGE:

Contextual Info: M74HC03 QUAD 2-INPUT OPEN DRAIN NAND GATE • ■ ■ ■ ■ ■ HIGH SPEED: tPD = 8ns TYP. at VCC = 6V LOW POWER DISSIPATION: ICC = 1µA(MAX.) at TA=25°C HIGH NOISE IMMUNITY: VNIH = V NIL = 28 % VCC (MIN.) BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL WIDE OPERATING VOLTAGE RANGE:

74AC16245

Abstract: 74AC16245TTR TSSOP48
Contextual Info: 74AC16245 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS NON INVERTED • ■ ■ ■ ■ ■ ■ ■ ■ HIGH SPEED: tPD = 4.5 ns (TYP.) at VCC = 5V LOW POWER DISSIPATION: ICC = 4 µA (MAX.) at TA=25°C HIGH NOISE IMMUNITY: VNIH = V NIL = 28% VCC (MIN.) POWER DOWN PROTECTION ON INPUTS

74AC16245

Abstract: 74AC16245TTR TSSOP48
Contextual Info: 74AC16245 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS NON INVERTED • ■ ■ ■ ■ ■ ■ ■ ■ HIGH SPEED: tPD = 4.5 ns (TYP.) at VCC = 5V LOW POWER DISSIPATION: ICC = 4 µA (MAX.) at TA=25°C HIGH NOISE IMMUNITY: VNIH = VNIL = 28% VCC (MIN.) POWER DOWN PROTECTION ON INPUTS

Contextual Info: M74HCT245 OCTAL BUS TRANSCEIVER WITH 3 STATE OUTPUTS NON INVERTED • ■ ■ ■ ■ ■ HIGH SPEED: tPD = 13ns (TYP.) at VCC = 4.5V LOW POWER DISSIPATION: ICC = 4µA(MAX.) at TA=25°C COMPATIBLE WITH TTL OUTPUTS : VIH = 2V (MIN.) VIL = 0.8V (MAX) SYMMETRICAL OUTPUT IMPEDANCE:

74V2G03

Abstract: 74V2G03STR
Contextual Info: 74V2G03 DUAL 2-INPUT OPEN DRAIN NAND GATE • ■ ■ ■ ■ ■ HIGH SPEED: tPD = 3.9ns TYP. at VCC = 5V LOW POWER DISSIPATION: ICC = 1µA(MAX.) at TA = 25°C HIGH NOISE IMMUNITY: VNIH = VNIL = 28% VCC (MIN.) POWER DOWN PROTECTION ON INPUTS OPERATING VOLTAGE RANGE:

M54HC03

Abstract: M54HC03D M54HC03K
Contextual Info: M54HC03 RAD-HARD QUAD 2-INPUT OPEN DRAIN NAND GATE • ■ ■ ■ ■ ■ ■ ■ ■ ■ HIGH SPEED: tPD = 8ns TYP. at VCC = 6V LOW POWER DISSIPATION: ICC = 1µA(MAX.) at TA=25°C HIGH NOISE IMMUNITY: VNIH = VNIL = 28% VCC (MIN.) BALANCED PROPAGATION DELAYS:

M74HC266B1R

Abstract: M74HC266 M74HC266M1R M74HC266RM13TR M74HC266TTR TSSOP14 M74HC266B1
Contextual Info: M74HC266 QUAD EXCLUSIVE NOR GATE WITH OPEN DRAIN • ■ ■ ■ ■ HIGH SPEED: tPD = 10ns TYP. at VCC = 6V LOW POWER DISSIPATION: ICC = 1µA(MAX.) at TA=25°C HIGH NOISE IMMUNITY: VNIH = V NIL = 28 % VCC (MIN.) WIDE OPERATING VOLTAGE RANGE: VCC (OPR) = 2V to 6V