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    PLB4ARB8M

    Abstract: ibm sram plb4
    Contextual Info: IBM SRAM Memory Controller to PLB4 SRAMMC2PLB4 Overview • Optional soft-error detection via parity checking. The SRAM Memory Controller to PLB4 (SRAMMC2PLB4) transfers data between the Processor Local Bus (PLB4) and embedded SRAM. • The following PLB slave cycles:


    Original     		64-bit16-byte128-bitpb-01+3plb4arb8mibm sramplb4 PDF

    Cu-08

    Abstract: SA15-5839-02 SRAMMC2PLB4 SA-14-2525
    Contextual Info: IBM Title Page SRAM Memory Controller to PLB4 SRAMMC2PLB4 Core Databook SA15-5839-02 Revision 2 March 31, 2006 IBM Copyright and Disclaimer Copyright International Business Machines Corporation 2005, 2006 All Rights Reserved Printed in the United States of America March, 2006


    Original     		sa15-5839-0264-bit32-bitcu-08+2srammc2plb4sa-14-2525 PDF