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PLB4ARB8M Datasheets (1)

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IBM

Part	ECAD Model	Manufacturer	Description	Datasheet Type	PDF	PDF Size	Page count
PLB4ARB8M		IBM	Arbiter Core, High performance core for highly integrated Core, ASIC systems	Original	PDF	23.49KB	2

PLB4ARB8M Datasheets Context Search

Catalog Datasheet	Type	Document Tags	PDF
PLB4ARB8M Abstract: Non-Pipelined processor Contextual Info: 128-bit PLB Arbiter Core, 8 Masters C27E503_PLB_128B_8M and PLB4ARB8M High performance core for highly integrated Core+ASIC systems Highlights The processor local bus is a high performance on-chip bus used in highly integrated Core+ASIC systems. The PLB supports read and write data	Original	128-bit c27e503 sa14-2579-01 plb4arb8m +1non-pipelined processor	PDF
PLB4ARB8M Abstract: ibm sram plb4 Contextual Info: IBM SRAM Memory Controller to PLB4 SRAMMC2PLB4 Overview • Optional soft-error detection via parity checking. The SRAM Memory Controller to PLB4 (SRAMMC2PLB4) transfers data between the Processor Local Bus (PLB4) and embedded SRAM. • The following PLB slave cycles:	Original	64-bit 16-byte 128-bit pb-01 +3plb4arb8m ibm sram plb4	PDF

Catalog Datasheet

Type

Document Tags

PDF

PLB4ARB8M

Abstract: Non-Pipelined processor
Contextual Info: 128-bit PLB Arbiter Core, 8 Masters C27E503_PLB_128B_8M and PLB4ARB8M High performance core for highly integrated Core+ASIC systems Highlights The processor local bus is a high performance on-chip bus used in highly integrated Core+ASIC systems. The PLB supports read and write data

Original

128-bit c27e503 sa14-2579-01 plb4arb8m +1

PDF

PLB4ARB8M

Abstract: ibm sram plb4
Contextual Info: IBM SRAM Memory Controller to PLB4 SRAMMC2PLB4 Overview • Optional soft-error detection via parity checking. The SRAM Memory Controller to PLB4 (SRAMMC2PLB4) transfers data between the Processor Local Bus (PLB4) and embedded SRAM. • The following PLB slave cycles:

Original

64-bit 16-byte 128-bit pb-01 +3

PDF