SRAM SERIAL Search Results

FPGA with i2c eeprom

Abstract: EEPROM I2C atmel ,vhdl code for implementation of eeprom verilog code for i2c vhdl code for i2c interface in fpga verilog code for implementation of eeprom vhdl code for i2c 256X8 ram A3P400 APA150
Contextual Info: Application Note AC214 Embedded SRAM Initialization Using External Serial EEPROM Introduction Embedded SRAM blocks have become common in FPGA design. Since SRAM is a volatile memory type, the stored data vanishes in the absence of power. When power is restored, the memory is empty. As many

MC19

Contextual Info: INTEGRATED CIRCUITS PZ3320C/PZ3320N 320 macrocell SRAM CPLD Preliminary specification IC27 Data Handbook Philips Semiconductors 1998 Jul 22 Philips Semiconductors Preliminary specification 320 macrocell SRAM CPLD PZ3320C/PZ3320N FEATURES DESCRIPTION • 320 macrocell SRAM based CPLD

Contextual Info: Philips Semiconductors Product specification 320 macrocell SRAM CPLD PZ3320C/PZ3320N FEATURES DESCRIPTION • 320 macrocell SRAM based CPLD The PZ3320 device is a m em ber of the CoolRunner fam ily of high-density SRAM -based CPLDs Com plex Program mable Logic

atmel 1138* datasheet

Abstract: atmel AT94K manual capacitor CTC1 fif6 32X4 AT17 AT40K AT94K AT94K10 AT94K20
Contextual Info: Features • Monolithic Field Programmable System Level Integrated Circuit • • • • • • • • • • • • • • – AT40K SRAM-based FPGA with Embedded High-performance RISC AVR Core and Extensive Data and Instruction SRAM 10,000 to 40,000 Gates of Patented SRAM-based AT40K FPGA with FreeRAM

RCM3315

Abstract: RCM3305 rj 47
Contextual Info: RCM3305 RabbitCore TM MODELS | 3305 | 3315 | Microprocessor Core Module Key Features ƒ Rabbit 3000 @ 44.2 MHz ƒ 10/100Base-T Ethernet, RJ-45 ƒ 4 MByte – 8 MByte Serial Flash ƒ 512K SRAM Program 512K SRAM (Data) ƒ Up to 512K Flash ƒ 3.3 V Operation

AC307

Abstract: SPARTAN 3E STARTER BOARD L262144 memory 2114 XILINX/SPARTAN 3E STARTER BOARD AFS090 generic SPI AFS-EVAL
Contextual Info: Application Note AC307 Configuring SRAM FPGAs Using Actel Fusion Introduction Due to the nature of SRAM technology, SRAM-based FPGAs are volatile and lose their configuration when powered off, so they must be reconfigured at every power-up. Hence, almost every system using SRAMbased FPGAs contains an additional nonvolatile memory, such as flash PROM or EEPROM, to store the

K7A803200B

Abstract: K7A803600B K7A801800B
Contextual Info: K7A803600B K7A803200B K7A801800B PRELIMINARY 256Kx36 & 256Kx32 & 512Kx18 Synchronous SRAM Document Title 256Kx36 & 256Kx32 & 512Kx18-Bit Synchronous Pipelined Burst SRAM Revision History Rev. No. 0.0 0.1 0.2 History Draft Date Remark Initial draft 1. Delete pass- through

Contextual Info: CY7C1411KV18, CY7C1426KV18 CY7C1413KV18, CY7C1415KV18 36-Mbit QDR II SRAM 4-Word Burst Architecture 36-Mbit QDR® II SRAM 4-Word Burst Architecture Features Configurations Separate independent read and write data ports ❐ Supports concurrent transactions

CY7C1512KV18-250BZXI

Contextual Info: CY7C1510KV18, CY7C1525KV18 CY7C1512KV18, CY7C1514KV18 72-Mbit QDR II SRAM 2-Word Burst Architecture 72-Mbit QDR® II SRAM 2-Word Burst Architecture Features Configurations Separate independent read and write data ports ❐ Supports concurrent transactions

K7P801866B

Abstract: K7P801866B-HC33 K7P803666B SA12 SA13
Contextual Info: K7P803666B K7P801866B 256Kx36 & 512Kx18 SRAM Document Title 256Kx36 & 512Kx18 Synchronous Pipelined SRAM Revision History Rev. No. History Draft Date Remark Rev. 0.0 - Initial Document. June. 2000 Advance Rev. 0.1 - ZQ tolerance changed from 10% to 15% Aug. 2000

EPC1441PI8

Contextual Info: Configuration Devices for SRAM-Based LUT Devices CF52005-3.0 Datasheet This datasheet describes configuration devices for SRAM-based look-up table LUT devices. Supported Devices Table 1 lists the supported Altera  configuration devices. Table 1. Altera Configuration Devices

K7P161866A

Abstract: K7P161866A-HC25 K7P161866A-HC30 K7P161866A-HC33 K7P163666A K7P163666A-HC25 K7P163666A-HC30 K7P163666A-HC33 SA13 SA18
Contextual Info: K7P163666A K7P161866A 512Kx36 & 1Mx18 SRAM Document Title 512Kx36 & 1Mx18 Synchronous Pipelined SRAM Revision History Draft Date Remark - Initial Document Dec. 2001 Advance - Absolute maximum ratings are changed VDD : 2.815 - > 3.13 VDDQ : 2.815 - > 2.4 VTERM : 2.815 - > VDDQ+0.5 2.4V MAX

Contextual Info:  CY7C1311KV18, CY7C1911KV18 CY7C1313KV18, CY7C1315KV18 18-Mbit QDR II SRAM Four-Word Burst Architecture 18-Mbit QDR® II SRAM Four-Word Burst Architecture Features Configurations Separate independent read and write data ports ❐ Supports concurrent transactions

CIRCUIT SCHEMATIC CAR ECU

Abstract: SF126 ADUC7030 ADuC703x DDI0029G, ARM7TDMI Technical Reference Manual DDI0029G LSB16 adi please confirm the manufacturing date from the serial number recorded on the product
Contextual Info: Integrated Precision Battery Sensor For Automotive ADuC7030/ADuC7033 Preliminary Technical Data FEATURES Memory 32 kbytes Flash/EE memory, 4 kbytes SRAM ADuC7030 96 kbytes Flash/EE memory, 6 kbytes SRAM (ADuC7033) 10 kcycles Flash/EE endurance, 20 years Flash/EE retention

CY7C15632KV18

Abstract: 3M Touch Systems
Contextual Info: CY7C15632KV18 72-Mbit QDR II+ SRAM Four-Word Burst Architecture 2.5 Cycle Read Latency 72-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) Features Configurations Separate Independent Read and Write Data Ports ❐ Supports concurrent transactions

CY7C1612KV18

Contextual Info: CY7C1625KV18 CY7C1612KV18, CY7C1614KV18 144-Mbit QDR II SRAM 2-Word Burst Architecture 144-Mbit QDR ® II SRAM 2-Word Burst Architecture Features Configurations Separate independent read and write data ports ❐ Supports concurrent transactions CY7C1625KV18 – 16 M x 9

CY7C1412KV18-250BZXC

Abstract: CY7C1425KV18 CY7C1412KV18-250BZC CY7C1414KV18
Contextual Info: CY7C1425KV18 CY7C1412KV18, CY7C1414KV18 36-Mbit QDR II SRAM 2-Word Burst Architecture 36-Mbit QDR® II SRAM 2-Word Burst Architecture Features Configurations Separate independent read and write data ports ❐ Supports concurrent transactions CY7C1425KV18 – 4 M x 9

SAMSUNG MCP

Abstract: MCP NAND
Contextual Info: Preliminary MCP MEMORY K5P2881BCM Document Title Multi-Chip Package MEMORY 128M Bit 16Mx8 Nand Flash Memory / 8M Bit (512Kx16) Full CMOS SRAM Revision History Revision No. History Draft Date Remark 0.0 Initial draft. - 128M NAND Flash C-die - 8M SRAM B-die

K7Q161882A

Abstract: K7Q161882A-FC10 K7Q161882A-FC13 K7Q161882A-FC15 K7Q163682A K7Q163682A-FC10 K7Q163682A-FC13 K7Q163682A-FC15 din 6p IR 10D 9F
Contextual Info: K7Q163682A K7Q161882A 512Kx36 & 1Mx18 QDRTM b2 SRAM Document Title 512Kx36-bit, 1Mx18-bit QDRTM SRAM Revision History History Draft Date Remark 0.0 1. Initial document. May, 22 2001 Advance 0.1 1. Icc, Isb addition 2. 1.8V Vddq addition 3. Speed bin change

FullFlex36

Abstract: CYDXXS36V18 400 OHM RESISTOR DQ67
Contextual Info: CYDXXS72V18 CYDXXS36V18 CYDXXS18V18 FullFlex Synchronous SDR Dual Port SRAM FullFlex™ Synchronous SDR Dual Port SRAM Features Functional Description • True dual port memory enables simultaneous access the shared array from each port ■ Synchronous pipelined operation with single data rate SDR

CY7C25632

Abstract: 3M Touch Systems
Contextual Info: CY7C25632KV18 CY7C25652KV18 72-Mbit QDR II+ SRAM Four-Word Burst Architecture 2.5 Cycle Read Latency with ODT 72-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT Features • JTAG 1149.1 compatible test access port ■

Contextual Info: CY7C1525KV18 CY7C1512KV18 CY7C1514KV18 72-Mbit QDR II SRAM Two-Word Burst Architecture 72-Mbit QDR® II SRAM Two-Word Burst Architecture Features Configurations Separate independent read and write data ports ❐ Supports concurrent transactions CY7C1525KV18 – 8 M x 9

A65H73361

Abstract: A65H83181 SA10 SA11 SA12 SA13 SA15
Contextual Info: A65H73361/A65H83181 Series 128K x 36 & 256K x 18 Late Write Synchronous Fast SRAM with Pipelined Data Output Preliminary Document Title 128K x 36 & 256K x 18 Late Write Synchronous Fast SRAM with Pipelined Data Output Revision History Rev. No. 2.0 PRELIMINARY

Contextual Info: CY7C2245KV18 36-Mbit QDR II+ SRAM Four-Word Burst Architecture 2.0 Cycle Read Latency with ODT 36-Mbit QDR® II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency) with ODT Features Configurations • Separate independent read and write data ports