SRAM SERIAL Search Results

28F3202C3

Abstract: 29066
Contextual Info: PRODUCT PREVIEW 3 VOLT ADVANCED+ STACKED CHIP SCALE PACKAGE MEMORY 16-Mbit Flash + 2-Mbit SRAM - 28F1602C3 16-Mbit Flash + 4-Mbit SRAM - 28F1604C3 32-Mbit Flash + 4-Mbit SRAM - 28F3204C3 32-Mbit Flash + 2-Mbit SRAM - 28F3202C3 ! Flash Memory Plus SRAM

GVT71128DA36

Abstract: GVT71256DA18
Contextual Info: ADVANCE INFORMATION GALVANTECH, INC. GVT71128DA36/GVT71256DA18 128K X 36/256K X 18 SYNCHRONOUS SRAM SYNCHRONOUS BURST SRAM PIPELINED OUTPUT 128K x 36 SRAM 256K x 18 SRAM +3.3V SUPPLY, FULLY REGISTERED FEATURES GENERAL DESCRIPTION • • • • • The Galvantech Synchronous Burst SRAM family

23K256

Abstract: 8631 23A256 23K640 256 kbyte Low Power Serial SRAM 6166 ram pic with spi
Contextual Info: Serial SRAM Memory Serial SRAM Memory Family www.microchip.com/SRAM Serial SRAM Memory Do you need more RAM in your application? Does it need to be small, cheap, fast and low power? Are you completing a design and need just a little more volatile memory? Do you need a simple, inexpensive way to add RAM without

GVT71256T18

Abstract: DQ974
Contextual Info: ADVANCE INFORMATION GALVANTECH, INC. SYNCHRONOUS CACHE TAG SRAM PIPELINED OUTPUT GVT71256T18 256K X 18 SYNCHRONOUS TAG SRAM 256K x 18 SRAM +3.3V SUPPLY WITH CLOCKED REGISTERED INPUTS FEATURES GENERAL DESCRIPTION • • • • • • The Galvantech Synchronous Burst SRAM family

FPGA with i2c eeprom

Abstract: EEPROM I2C atmel ,vhdl code for implementation of eeprom verilog code for i2c vhdl code for i2c interface in fpga verilog code for implementation of eeprom vhdl code for i2c 256X8 ram A3P400 APA150
Contextual Info: Application Note AC214 Embedded SRAM Initialization Using External Serial EEPROM Introduction Embedded SRAM blocks have become common in FPGA design. Since SRAM is a volatile memory type, the stored data vanishes in the absence of power. When power is restored, the memory is empty. As many

100-PIN

Abstract: GVT71256ZC36 GVT71512ZC18
Contextual Info: ADVANCE INFORMATION GVT71512ZC36/GVT71A24ZC18 512K X 36/1M X 18 ZBL SRAM GALVANTECH, INC. SYNCHRONOUS ZBL SRAM PIPELINED OUTPUT 512K x 36 SRAM 1M x 18 SRAM +3.3V SUPPLY, +3.3V or +2.5V I/O FEATURES GENERAL DESCRIPTION • The GVT71512ZC36 and GVT71A24ZC18 SRAMs are

Equivalent of sw2 354

Abstract: sw2 354 8080 microprocessor Architecture Diagram cmos power TCP 8108 oasis F-173
Contextual Info: 8 Megabit Flash + 2 Megabit SRAM ComboMemory SST32LH802 Advance Information FEATURES: • Organized as 512K x16 Flash + 128K x16 SRAM or 512K x8 x2 Flash + 128K x8 x2 SRAM • Single 3.0-3.6V Read and Write Operations • Concurrent Operation – Read from or write to SRAM while

Contextual Info: CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F 18-Mbit 512 K x 36/1 M × 18 Pipelined SRAM 18-Mbit (512 K × 36/1 M × 18) Pipelined SRAM Features Functional Description The CY7C1380D/CY7C1382D/CY7C1380F/CY7C1382F[1] SRAM integrates 524,288 × 36 and 1,048,576 × 18 SRAM cells

Contextual Info: CY7C1380D, CY7C1380F CY7C1382D, CY7C1382F 18-Mbit 512 K x 36/1 M × 18 Pipelined SRAM 18-Mbit (512 K × 36/1 M × 18) Pipelined SRAM Features Functional Description The CY7C1380D/CY7C1380F/CY7C1382D/CY7C1382F[1] SRAM integrates 524,288 × 36 and 1,048,576 × 18 SRAM cells

MC19

Contextual Info: INTEGRATED CIRCUITS PZ3320C/PZ3320N 320 macrocell SRAM CPLD Preliminary specification IC27 Data Handbook Philips Semiconductors 1998 Jul 22 Philips Semiconductors Preliminary specification 320 macrocell SRAM CPLD PZ3320C/PZ3320N FEATURES DESCRIPTION • 320 macrocell SRAM based CPLD

Contextual Info: QDR SRAM CONSORTIUM RELEASES SPECIFICATIONS High-Bandwidth Networking SRAM Specifications Are Now Available SAN JOSE, Calif., February 16, 2000 - The QDR™ SRAM Consortium, consisting of Cypress Semiconductor NYSE: CY ; IDT (Nasdaq: IDTI); and Micron Technology Inc. (NYSE:

CY7C1380D

Abstract: AN1064 CY7C1380F CY7C1382D CY7C1382F
Contextual Info: CY7C1380D, CY7C1380F CY7C1382D, CY7C1382F 18-Mbit 512K x 36/1M x 18 Pipelined SRAM Functional Description [1] Features • Supports bus operation up to 250 MHz The CY7C1380D/CY7C1382D/CY7C1380F/CY7C1382F SRAM integrates 524,288 x 36 and 1,048,576 x 18 SRAM

Contextual Info: Philips Semiconductors Preliminary specification 320 macroceil SRAM CPLD PZ3320C/PZ3320N FEATURES DESCRIPTION • 320 macrocell SRAM based CPLD The PZ3320 device is a member of the CoolRunner family of high-density SRAM-based CPLDs Complex Programmable Logic

Atmel 0347

Abstract: I0358 Atmel 0342 avr aa26 FIF12 4Kx8 Dual-Port Static RAM capacitor CTC1 sbc hc 8352 147P3 AT40K
Contextual Info: Features • Monolithic Field Programmable System Level Integrated Circuit - AT40K SRAM-based FPGA with Embedded High-performance RISC AVR Core and Extensive Data and Instruction SRAM • 10,000 to 40,000 Gates of Patented SRAM-based AT40K FPGA with FreeRAM

EPCS16

Abstract: epc1213 EPCS4 EPF10K100 EP20K200E EP20K400E EP20K60E EP2S15 EP2S30 EP2S60
Contextual Info: Chapter 1. Altera Configuration Devices CF52001-2.0 Introduction During device operation, Altera FPGAs store configuration data in SRAM cells. Because SRAM memory is volatile, the SRAM cells must be loaded with configuration data each time the device powers up. You can

K02AE

Contextual Info: Features • Monolithic Field Programmable System Level Integrated Circuit - AT40K SRAM-based FPGA with Embedded High-performance RISC AVR Core and Extensive Data and Instruction SRAM • 10,000 to 40,000 Gates of Patented SRAM-based AT40K FPGA with FreeRAM

EPCS64

Abstract: EPCS16 epc1213 EP20K200E EP20K400E EP20K60E EP2S15 EP2S30 EP2S60 EPC1441
Contextual Info: 1. Altera Configuration Devices CF52001-2.3 Introduction During device operation, Altera FPGAs store configuration data in SRAM cells. Because SRAM memory is volatile, the SRAM cells must be loaded with configuration data each time the device powers up. You can

AN1064

Abstract: CY7C1380D CY7C1380F CY7C1382D CY7C1382F
Contextual Info: CY7C1380D, CY7C1380F CY7C1382D, CY7C1382F 18-Mbit 512K x 36/1M x 18 Pipelined SRAM Functional Description [1] Features • Supports bus operation up to 250 MHz The CY7C1380D/CY7C1382D/CY7C1380F/CY7C1382F SRAM integrates 524,288 x 36 and 1,048,576 x 18 SRAM

a20 tssop-8

Abstract: HN58X24512FPIAG Hitachi DSA00279 csp48
Contextual Info: HITACHI Low Power SRAM and EEPROM HITACHI Low Power SRAMs and EEPROM February, 2002 Product Marketing Team System Memory Business Unit Semiconductor and Integrated Circuits Hitachi, Ltd. HITACHI Low Power SRAM and EEPROM HITACHI Low Power SRAMs HITACHI Low Power SRAM and EEPROM

AN1064

Abstract: CY7C1380D CY7C1380F CY7C1382D CY7C1382F INTEL-PENTIUM 32D10
Contextual Info: CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F 18-Mbit 512K x 36/1M x 18 Pipelined SRAM Features Functional Description The CY7C1380D/CY7C1382D/CY7C1380F/CY7C1382F[1] SRAM integrates 524,288 x 36 and 1,048,576 x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit

100-PIN

Abstract: GVT71256ZB36 GVT71512ZB18 4g81
Contextual Info: PRELIMINARY GVT71256ZB36/GVT71512ZB18 256K X 36/512K X 18 ZBL SRAM GALVANTECH, INC. SYNCHRONOUS 256K x 36 SRAM ZBL SRAM 512K x 18 SRAM FLOW-THRU OUTPUT +3.3V SUPPLY, +3.3V or +2.5V I/O FEATURES • • • • • • • • • • • • • • • Zero Bus Latency, no dead cycles between write and read

AN1064

Abstract: CY7C1386D CY7C1386F CY7C1387D CY7C1387F
Contextual Info: CY7C1386D, CY7C1386F CY7C1387D, CY7C1387F 18-Mbit 512K x 36/1 Mbit x 18 Pipelined DCD Sync SRAM Functional Description [1] Features • Supports bus operation up to 250 MHz The CY7C1386D/CY7C1387D/CY7C1386F/CY7C1387F SRAM integrates 512K x 36/1M x 18 SRAM cells with

AN1064

Abstract: CY7C1386D CY7C1386F CY7C1387D CY7C1387F
Contextual Info: CY7C1386D, CY7C1386F CY7C1387D, CY7C1387F 18-Mbit 512K x 36/1 Mbit x 18 Pipelined DCD Sync SRAM Functional Description [1] Features • Supports bus operation up to 250 MHz The CY7C1386D/CY7C1387D/CY7C1386F/CY7C1387F SRAM integrates 512K x 36/1M x 18 SRAM cells with

CY7C1366C

Abstract: CY7C1367C
Contextual Info: CY7C1366C/CY7C1367C 9-Mbit 256K x 36/512K x 18 Pipelined DCD Sync SRAM Features Functional Description The CY7C1366C/CY7C1367C SRAM[1] integrates 256K x 36 and 512K x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst