CY7C1386D Search Results

Contextual Info: CY7C1386D CY7C1387D 18-Mbit 512 K x 36/1 M × 18 Pipelined DCD Sync SRAM 18-Mbit (512 K × 36/1 M × 18) Pipelined DCD Sync SRAM Features Functional Description • Supports bus operation up to 200 MHz ■ Available speed grades are 200, and 167 MHz ■

Contextual Info: CY7C1386D CY7C1387D 18-Mbit 512 K x 36/1 M × 18 Pipelined DCD Sync SRAM 18-Mbit (512 K × 36/1 M × 18) Pipelined DCD Sync SRAM Features Functional Description • Supports bus operation up to 200 MHz ■ Available speed grades are 200, and 167 MHz ■

Contextual Info: CY7C1386D CY7C1387D PRELIMINARY 18-Mbit 512K x 36/1M x 18 Pipelined DCD Sync SRAM Functional Description[1] Features • Supports bus operation up to 250 MHz • Available speed grades are 250, 225, 200 and 167 MHz • Registered inputs and outputs for pipelined operation

Contextual Info: THIS SPEC IS OBSOLETE Spec No: 38-05548 Spec Title: CY7C1386DV25/CY7C1387DV25/CY7C1386FV25/ CY7C1387FV25 18-Mbit 512K x 36/1M x 18 Pipelined DCD Sync SRAM Sunset Owner: N Vijay Kumar (VKN) Replaced by: None CY7C1386DV25, CY7C1386FV25 CY7C1387DV25, CY7C1387FV25

CY7C1387D

Abstract: CY7C1386D
Contextual Info: CY7C1386D CY7C1387D PRELIMINARY 18-Mbit 512K x 36/1 Mbit x 18 Pipelined DCD Sync SRAM Functional Description[1] Features • Supports bus operation up to 250 MHz • Available speed grades are 250, 200, and 167 MHz • Registered inputs and outputs for pipelined operation

CY7C1386D

Abstract: CY7C1387D
Contextual Info: PRELIMINARY CY7C1386D CY7C1387D 18-Mbit 512K x 36/1 Mbit x 18 Pipelined DCD Sync SRAM Functional Description[1] Features • Supports bus operation up to 250 MHz • Available speed grades are 250, 200 and 167 MHz • Registered inputs and outputs for pipelined operation

Contextual Info: CY7C1386DV25 CY7C1387DV25 PRELIMINARY 18-Mbit 512K x 36/1M x 18 Pipelined DCD Sync SRAM Functional Description[1] Features • Supports bus operation up to 250 MHz • Available speed grades are 250, 225, 200, and 167 MHz • Registered inputs and outputs for pipelined operation

Contextual Info: CY7C1386DV25 CY7C1387DV25 PRELIMINARY 18-Mbit 512K x 36/1M x 18 Pipelined DCD Sync SRAM Functional Description[1] Features • Supports bus operation up to 250 MHz • Available speed grades are 250, 200 and 167 MHz • Registered inputs and outputs for pipelined operation

Contextual Info: CY7C1386DV25, CY7C1386FV25 CY7C1387DV25, CY7C1387FV25 18-Mbit 512K x 36/1M x 18 Pipelined DCD Sync SRAM Functional Description [1] Features • Supports bus operation up to 250 MHz The CY7C1386DV25/CY7C1387DV25/CY7C1386FV25/ CY7C1387FV25 SRAM integrates 512K x 36 and 1M x 18

Contextual Info: CY7C1386D CY7C1387D 18-Mbit 512K x 36/1 Mbit x 18 Pipelined DCD Sync SRAM Functional Description[1] Features • Supports bus operation up to 250 MHz • Available speed grades are 250, 200 and 167 MHz • Registered inputs and outputs for pipelined operation

AN1064

Abstract: CY7C1386D CY7C1386F CY7C1387D CY7C1387F
Contextual Info: CY7C1386D, CY7C1386F CY7C1387D, CY7C1387F 18-Mbit 512K x 36/1 Mbit x 18 Pipelined DCD Sync SRAM Functional Description [1] Features • Supports bus operation up to 250 MHz The CY7C1386D/CY7C1387D/CY7C1386F/CY7C1387F SRAM integrates 512K x 36/1M x 18 SRAM cells with

CY7C1386D

Abstract: CY7C1387D
Contextual Info: PRELIMINARY CY7C1386D CY7C1387D 18-Mbit 512K x 36/1 Mbit x 18 Pipelined DCD Sync SRAM Functional Description[1] Features • Supports bus operation up to 250 MHz • Available speed grades are 250, 200 and 167 MHz • Registered inputs and outputs for pipelined operation

AN1064

Abstract: CY7C1386D CY7C1386F CY7C1387D CY7C1387F
Contextual Info: CY7C1386D, CY7C1386F CY7C1387D, CY7C1387F 18-Mbit 512 K x 36/1-Mbit × 18 Pipelined DCD Sync SRAM 18-Mbit (512 K × 36/1-Mbit × 18) Pipelined DCD Sync SRAM Features Functional Description • Supports bus operation up to 250 MHz ■ Available speed grades are 250, 200, and 167 MHz

Contextual Info: CY7C1386D CY7C1387D 18-Mbit 512 K x 36/1 M × 18 Pipelined DCD Sync SRAM 18-Mbit (512 K × 36/1 M × 18) Pipelined DCD Sync SRAM Features Functional Description • Supports bus operation up to 200 MHz ■ Available speed grades are 200, and 167 MHz ■

Contextual Info: CY7C1386DV25 CY7C1387DV25 PRELIMINARY 18-Mbit 512K x 36/1M x 18 Pipelined DCD Sync SRAM Functional Description[1] Features • Supports bus operation up to 250 MHz • Available speed grades are 250, 200, and 167 MHz • Registered inputs and outputs for pipelined operation

Contextual Info: CY7C1386D CY7C1387D 18-Mbit 512K x 36/1 Mbit x 18 Pipelined DCD Sync SRAM Functional Description[1] Features • Supports bus operation up to 250 MHz • Available speed grades are 250, 200 and 167 MHz • Registered inputs and outputs for pipelined operation

AN1064

Abstract: CY7C1386D CY7C1386F CY7C1387D CY7C1387F
Contextual Info: CY7C1386D, CY7C1386F CY7C1387D, CY7C1387F 18-Mbit 512 K x 36/1 M × 18 Pipelined DCD Sync SRAM 18-Mbit (512 K × 36/1 M × 18) Pipelined DCD Sync SRAM Features Functional Description • Supports bus operation up to 250 MHz The CY7C1386D/CY7C1387D/CY7C1386F/CY7C1387F

CY7C1366C

Abstract: CY7C1386DV25 CY7C1387DV25 67L125
Contextual Info: CY7C1386DV25 CY7C1387DV25 PRELIMINARY 18-Mbit 512K x 36/1M x 18 Pipelined DCD Sync SRAM Functional Description[1] Features • Supports bus operation up to 250 MHz • Available speed grades are 250, 200, and 167 MHz • Registered inputs and outputs for pipelined operation

Contextual Info: CY7C1386D CY7C1387D 18-Mbit 512 K x 36/1 M × 18 Pipelined DCD Sync SRAM 18-Mbit (512 K × 36/1 M × 18) Pipelined DCD Sync SRAM Features Functional Description • Supports bus operation up to 200 MHz ■ Available speed grades are 200, and 167 MHz ■

AN1064

Abstract: CY7C1386DV25 CY7C1386FV25 CY7C1387DV25 CY7C1387FV25
Contextual Info: CY7C1386DV25, CY7C1386FV25 CY7C1387DV25, CY7C1387FV25 18-Mbit 512K x 36/1M x 18 Pipelined DCD Sync SRAM Functional Description [1] Features • Supports bus operation up to 250 MHz The CY7C1386DV25/CY7C1387DV25/CY7C1386FV25/ CY7C1387FV25 SRAM integrates 512K x 36 and 1M x 18

Contextual Info: CY7C1386DV25 CY7C1387DV25 18-Mbit 512K x 36/1M x 18 Pipelined DCD Sync SRAM Functional Description[1] Features • Supports bus operation up to 250 MHz • Available speed grades are 250, 200 and 167 MHz • Registered inputs and outputs for pipelined operation

Contextual Info: CY7C1386D CY7C1387D 18-Mbit 512 K x 36/1 M × 18 Pipelined DCD Sync SRAM 18-Mbit (512 K × 36/1 M × 18) Pipelined DCD Sync SRAM Features Functional Description • Supports bus operation up to 200 MHz ■ Available speed grades are 200, and 167 MHz ■

AN1064

Abstract: CY7C1386F CY7C1387F
Contextual Info: CY7C1386D/CY7C1386F CY7C1387D/CY7C1387F 18-Mbit 512K x 36/1 Mbit x 18 Pipelined DCD Sync SRAM Features Functional Description • Supports Bus Operation up to 250 MHz The CY7C1386D/CY7C1387D/CY7C1386F/CY7C1387F SRAM[1] integrates 512K x 36/1M x 18 SRAM cells with

schematic diagram atx Power supply 500w

Abstract: pioneer PAL 012A 1000w inverter PURE SINE WAVE schematic diagram 600va numeric ups circuit diagrams winbond bios 25064 TLE 9180 infineon smsc MEC 1300 nu TBE schematic diagram inverter 2000w DK55 circuit diagram of luminous 600va UPS
Contextual Info: QUICK INDEX NEW IN THIS ISSUE! Detailed Index - See Pages 3-24 Digital Signal Processors, iCoupler , iMEMS® and iSensor . . . . . 805, 2707, 2768-2769 Connectors, Cable Assemblies, IC Sockets . . . . . . . . . . . 28-568 RF Connectors . . . . . . . . . . . . . . . . . . . . . . Pages 454-455