CY7C1386DV25 Search Results

Contextual Info: THIS SPEC IS OBSOLETE Spec No: 38-05548 Spec Title: CY7C1386DV25/CY7C1387DV25/CY7C1386FV25/ CY7C1387FV25 18-Mbit 512K x 36/1M x 18 Pipelined DCD Sync SRAM Sunset Owner: N Vijay Kumar (VKN) Replaced by: None CY7C1386DV25, CY7C1386FV25 CY7C1387DV25, CY7C1387FV25

Contextual Info: CY7C1386DV25 CY7C1387DV25 PRELIMINARY 18-Mbit 512K x 36/1M x 18 Pipelined DCD Sync SRAM Functional Description[1] Features • Supports bus operation up to 250 MHz • Available speed grades are 250, 225, 200, and 167 MHz • Registered inputs and outputs for pipelined operation

Contextual Info: CY7C1386DV25 CY7C1387DV25 PRELIMINARY 18-Mbit 512K x 36/1M x 18 Pipelined DCD Sync SRAM Functional Description[1] Features • Supports bus operation up to 250 MHz • Available speed grades are 250, 200 and 167 MHz • Registered inputs and outputs for pipelined operation

Contextual Info: CY7C1386DV25, CY7C1386FV25 CY7C1387DV25, CY7C1387FV25 18-Mbit 512K x 36/1M x 18 Pipelined DCD Sync SRAM Functional Description [1] Features • Supports bus operation up to 250 MHz The CY7C1386DV25/CY7C1387DV25/CY7C1386FV25/ CY7C1387FV25 SRAM integrates 512K x 36 and 1M x 18

Contextual Info: CY7C1386DV25 CY7C1387DV25 PRELIMINARY 18-Mbit 512K x 36/1M x 18 Pipelined DCD Sync SRAM Functional Description[1] Features • Supports bus operation up to 250 MHz • Available speed grades are 250, 200, and 167 MHz • Registered inputs and outputs for pipelined operation

CY7C1366C

Abstract: CY7C1386DV25 CY7C1387DV25 67L125
Contextual Info: CY7C1386DV25 CY7C1387DV25 PRELIMINARY 18-Mbit 512K x 36/1M x 18 Pipelined DCD Sync SRAM Functional Description[1] Features • Supports bus operation up to 250 MHz • Available speed grades are 250, 200, and 167 MHz • Registered inputs and outputs for pipelined operation

AN1064

Abstract: CY7C1386DV25 CY7C1386FV25 CY7C1387DV25 CY7C1387FV25
Contextual Info: CY7C1386DV25, CY7C1386FV25 CY7C1387DV25, CY7C1387FV25 18-Mbit 512K x 36/1M x 18 Pipelined DCD Sync SRAM Functional Description [1] Features • Supports bus operation up to 250 MHz The CY7C1386DV25/CY7C1387DV25/CY7C1386FV25/ CY7C1387FV25 SRAM integrates 512K x 36 and 1M x 18

Contextual Info: CY7C1386DV25 CY7C1387DV25 18-Mbit 512K x 36/1M x 18 Pipelined DCD Sync SRAM Functional Description[1] Features • Supports bus operation up to 250 MHz • Available speed grades are 250, 200 and 167 MHz • Registered inputs and outputs for pipelined operation

CY7C1338-100AXC

Abstract: gvt7164d32q-6 CY7C1049BV33-12VXC CY7C1363C-133AC CY7C1021DV33-12ZXC CY7C1460AV25-200AXC CY7C1338G-100AC CY7C1041V33-12ZXC CY7C1460V33-200AXC CY7C1021DV33-10ZXC
Contextual Info: CYPRESS / GALVANTECH # - Connect pin 14 FT pin to Vss CY7C1019BV33-15VC GS71108AJ-12 & - Does not support 1.8V I/O CY7C1019BV33-15VXC GS71108AGJ-12 * - Tie down extra four I/Os with resistor CY7C1019BV33-15ZC GS71108ATP-12 CY7C1019BV33-15ZXC GS71108AGP-12