SPLIT CACHE Search Results

Contextual Info: ft fdt BiCameral CacheRAM™ 288K 16K x 9 x 2) FOR RISC CACHES PRELIMINARY IDT71B229S Integrated Devi ce Technology, Inc. FEATURES: DESCRIPTION: Supports the R3000, R3500 and R3001 to 40MHz Bicam eral organization-. — Split instruction/data cache support

79R3000

Contextual Info: Bicameral CacheRAM” 288K 16K x 9 x 2 FOR RISC CACHES PRELIMINARY IDT71B229S FEATURES: DESCRIPTION: • Supports the R3000 and R3001 to 40MHz • Bicam eral organization: — Split instruction/data cache support — No bank-switching timing contention

Contextual Info: AMDÎ1 AMD-K6 E High-Performance, AMD-K6 Embedded Processor DISTINCTIVE CHARACTERISTICS • Advanced 6-Issue RISC86 Superscalar Microarchitecture - Seven parallel specialized execution units ■ Large On-Chip Split 64-Kbyte Level-One L1 Cache - 32-Kbyte instruction cache with additional

k 2996

Abstract: s0322 ic dwe
Contextual Info: Integrated Device Technology, Inc. Bicameral CacheRAM™ 288K 16K X 9 X 2 FOR RISC CACHES FEATURES: PRELIMINARY IDT71B229S DESCRIPTION: • Supports the R 3000, R 350 0 and R3001 to 40 M H z • BiCameral organization: — Split instruction/data cache support

dc-dc converter 12v to 5v 3a

Abstract: T38-52 panasonic 1000uf 6.3v HIP5010 HIP5011 HIP5015 HIP5016 P55C schematic diagram dc-dc 2N7002CT
Contextual Info: A Flexible DC-DC Converter for Powering HighPerformance Microprocessors HIP5015EVAL2 Application Note August 1996 AN9625.1 Author: Greg J. Miller Introduction Some of the newer, high-performance microprocessors are migrating to a split voltage bus architecture - the processor

Contextual Info: AMDÎ1 AMD-K6 E High-Performance, AMD-K6 Embedded Processor DISTINCTIVE CHARACTERISTICS • Advanced 6-Issue RISC86 Superscalar M ic roa rch itectu re - Seven parallel specialized execution units ■ Large On-Chip Split 64-Kbyte Level-One L1 Cache - 32-Kbyte Instruction cache with additional

ST40 TOOLSET

Abstract: ADCS 7153464 ADCS 7225754 ST40 manual ADCS 7182230 7225754 ADCS 7181720 ADCS 7379953 STi5514 st20 C01032
Contextual Info: UM0340 User manual SuperH SH 32-bit RISC series SH-4, ST40 system architecture, volume 2: bus interfaces This manual describes the ST40 family system architecture. It is split into four volumes: ST40 System Architecture - Volume 1 System - ADCS 7153464.

PowerPC 60X Bus Interface controller

Abstract: EDO FLASH DIMMs 72 pin map 3222 82660 EDO FLASH DIMMs tagram TEA 2111 IBM27-82660 52 signals PowerPC 601 IBM powerpc
Contextual Info: PowerPC 60x Memory Controller and PCI Bridge IBM27-82660 Description Highlights General • Extensive programmability • Flexible and programmable error handling • Dual split bus structure CPU-PCI • Chipset options configured in register set • Two low-cost plastic quad flat packs

Contextual Info: Agilent Technologies E2929B PCI-X Exerciser and Analyzer Technical Overview Key Specifications • O to 133.4 MHz clock speed · 64 bit data and addressing · Exerciser option #300 with full capabilities, including split transactions and 1MB data memory and real-time

LA 7840

Abstract: E2925B E2929B PAR64 REQ64 FS2104 "network interface cards"
Contextual Info: Agilent Technologies E2929B PCI-X Exerciser and Analyzer Technical Overview Key Specifications • O to 133.4 MHz clock speed · 64 bit data and addressing · Exerciser option #300 with full capabilities, including split transactions and 1MB data memory and real-time

ACT5231

Abstract: ACT-5231PC-133F22C R4700 R5000 RM5231
Contextual Info: ACT5231 32-Bit Superscaler Microprocessor Features • Full militarized QED RM5231 microprocessor ■ Pinout compatible with popular RM5230 with split power sup plies 2.5V and 3.3V ■ Dual Issue superscalar microprocessor - can issue one integer and one floating-point instruction per cycle

Contextual Info: ADVANCE INFORMATION IDT71B229 Bicameral CacheRAM™ 256K-BIT 16K X 9 X 2 FOR RISC CACHES FEATURES: DESCRIPTION: • High speed supports fastest R 3 0 0 0 CPUs: — 15, 22, 28ns — Supports 33, 25 and 20 M H z • B icam eral organization: — Split instruction/data cache support,

ST40 TOOLSET

Abstract: ADCS 7225754 ADCS 7153464 adcs 7182230 st40 instruction set 7182230 ST40 System Architecture BAA31 st40 Application CPU ST40 manual ST40-C200
Contextual Info: UM0339 User manual SuperH SH 32-bit RISC series SH-4, ST40 system architecture, volume 1: system This manual describes the ST40 family system architecture. It is split into four volumes: ST40 System Architecture - Volume 1 System - ADCS 7153464. ST40 System Architecture - Volume 2 Bus Interfaces - ADCS 7181720.

IDT79R4000

Contextual Info: PRELIMINARY IDT7MP6048 IDT7MP6068 IDT79R4000 FLEXI-CACHE" DEVELOPMENT TOOL Integrated Device Technology, Inc. FEATURES c h a n g e certa in c h a ra c te ristics c a c h e s iz e , n u m b e r of w o rd s p e r line, a nd split vs. un ified o p era tio n of th e s e c o n d a ry c a c h e

weitek

Abstract: concept 21145 80486 circuit acc micro 386 weitek 1167
Contextual Info: WESTERN DIGITAL CORP 41E D B ‘Ì71&3Z& 000^021, 3 QldDC SYSTEMS LOGIC/PERIPHERAL T '- S Z - 'b T . - U WD6030 Cache/DRAM and Channel Control Device 3^ WESTERN DIGITAL X WESTERN D I G IT A L CORP M1E J> B cj7 1 ö 2 2 ö TAB LE OF CONTENTS 000^027 S EllilDC

SDC40

Contextual Info: WESTERN DIGITAL CORP =1710220 0001=205 T SIE D Advance Information EE6030 Cache/DRAM and Channel Control Device Complete compatibility with the IBM* Personal System/2* Models 70 and 80 Direct-Mapped Cache Controller Includes the following: Page Mode DRAM Controller

AD47

Abstract: Futurebus SIGNAL PATH designer qs6z
Contextual Info: TFB2055 FUTUREBUS+ DATA PATH FOR CACHE * Parallel-Protocol Support is Fully Compliant to IEEE Standard 896.1 Futurebus+ * Interfaces Easily to a Variety of Popular Microprocessors Such as SPARC", 680x0, 88xxx, and 80x86 * May Be Used in Conjunction With the

fe6500

Contextual Info: Advance Information FE6030 Cache/DRAM and Channel Control Device a □ Complete compatibility with the IBM* Personal System/2* Models 70 and 80 Direct-Mapped Cache Controller Includes the following: Page Mode DRAM Controller Memory Configuration Registers

"snoop filter"

Abstract: signal path designer
Contextual Info: TFB2051 FUTUREBUS+ DATA PATH FOR CACHE CONTROLLER JANUARY 1992 Provides Control Logic Necessary to Operate a Data Path for Cache TFB2055 on the Futurebus+ Parallel-Protocol Support is Fully Com pliant to IEEE Standard 896.1 /p,t,r- h ,ic .\ * * Provides Full Support for Futurebus+

MX116

Abstract: 4116 dram dram 4116 fe6500 weitek 80386 microprocessor pin out diagram 80386 Programming the 80386 pin out of 80386 microprocessor 80386 specification update
Contextual Info: Advance Information * FE6030 Cache/DRAM and Channel Control Device Complete compatibility with the IBM* Personal System/2* Models 70 and 80 Direct-Mapped Cache Controller Includes the following: Page Mode DRAM Controller Memory Configuration Registers Channel Controller

MCM4464

Contextual Info: MOTOROLA • SEMICONDUCTOR TECHNICAL DATA 1MB R4000 Secondary Cache Fast Static RAM Module Set Four MCM4464 modules comprise a full 1 MB of secondary cache for the R4000 processor. Each module contains nine MCM6709AJ fast static RAMs for a cache data size of 64K x 36. The tag portion, dependent on word line size,

44c256

Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA 4MB R4000 Secondary Cache Fast Static RAM Module Set Four MCM44256 modules comprise a full 4 MB of secondary cache for the R4000 processor. Each module contains nine MCM6729WJ fast static RAMs for a cache data size of 256K x 36. The tag portion, dependent on word line size,

74fbt2827

Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA MCM44256 Series 4MB R4000 Secondary Cache Fast Static RAM Module Set Four MCM44256 modules comprise a full 4 MB of secondary cache for the R4000 processor. Each module contains nine MCM6729WJ fast static RAMs for a cache data size of 256K x 36. The tag portion, dependent on word line size,

M44256

Abstract: 7779A
Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA MCM4464 Series 1MB R4000 Secondary Cache Fast Static RAM Module Set Four M C M 4464 m odules com prise a full 1 MB of secondary ca che fo r the R 4000 processor. Each m odule contains nine M C M 6709J fa st static R AM s for