SOT1089 Search Results

Contextual Info: Reflow soldering footprint Footprint information for reflow soldering of XSON8 package 0.15 8x SOT1089 0.25 (8×) 0.5 (8×) 0.7 1.4 0.6 (8×) Dimensions in mm solder paste = solder land 0.35 (3×) 1.4 solder resist occupied area www.nxp.com 2009 NXP B.V.

Contextual Info: XS ON 8 SOT1089 XSON8; Reel pack; SMD, 7" Q1/T1 Standard product orientation Orderable part number ending ,115 or X Ordering code 12NC ending 115 Rev. 1 — 23 April 2013 Packing information 1. Packing method Printed plano box Barcode label Reel Tape QA Seal

MARKING V7 6-PIN

Contextual Info: 74LVC3G14 Triple inverting Schmitt trigger with 5 V tolerant input Rev. 11 — 6 July 2012 Product data sheet 1. General description The 74LVC3G14 provides three inverting buffers with Schmitt trigger input. It is capable of transforming slowly changing input signals into sharply defined, jitter-free output signals.

Marking code V7

Contextual Info: 74LVC2G00 Dual 2-input NAND gate Rev. 11 — 22 June 2012 Product data sheet 1. General description The 74LVC2G00 provides a 2-input NAND gate function. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in a mixed 3.3 V and 5 V environment.

transistor SMD N02

Abstract: NVT2002DP NVT2002GD NVT2002GF NVT2002 JESD22-A114 JESD22-A115 NVT2001 NVT2001GM
Contextual Info: NVT2001; NVT2002 Bidirectional voltage level translator for open-drain and push-pull applications Rev. 1 — 30 August 2010 Product data sheet 1. General description The NVT2001/02 are bidirectional voltage level translators operational from 1.0 V to 3.6 V

74LVC2G86

Abstract: 74LVC2G86DC 74LVC2G86DP 74LVC2G86GM 74LVC2G86GT
Contextual Info: 74LVC2G86 Dual 2-input EXCLUSIVE-OR gate Rev. 8 — 19 October 2010 Product data sheet 1. General description The 74LVC2G86 provides a dual 2-input EXCLUSIVE-OR gate. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these

74LVC1G74DC

Abstract: 74LVC1G74 74LVC1G74DP 74LVC1G74GD 74LVC1G74GM 74LVC1G74GT
Contextual Info: 74LVC1G74 Single D-type flip-flop with set and reset; positive edge trigger Rev. 9 — 5 August 2010 Product data sheet 1. General description The 74LVC1G74 is a single positive edge triggered D-type flip-flop with individual data D inputs, clock (CP) inputs, set (SD) and reset (RD) inputs, and complementary Q and Q

74AUP2G157DC

Abstract: 74AUP2G157GT
Contextual Info: 74AUP2G157 Low-power 2-input multiplexer Rev. 4 — 30 July 2010 Product data sheet 1. General description The 74AUP2G157 is a single 2-input multiplexer which select data from two data inputs I0 and I1 under control of a common data select input (S). The state of the common data

74LVC3G07

Abstract: 74LVC3G07DC 74LVC3G07DP 74LVC3G07GM 74LVC3G07GT
Contextual Info: 74LVC3G07 Triple buffer with open-drain output Rev. 7 — 9 August 2010 Product data sheet 1. General description The 74LVC3G07 provides three non-inverting buffers. The output of the device is an open-drain and can be connected to other open-drain outputs to implement active-LOW wired-OR or active-HIGH wired-AND functions.

74LVC2G32

Abstract: 74LVC2G32DC 74LVC2G32DP 74LVC2G32GM 74LVC2G32GT XSON8 SOT1116
Contextual Info: 74LVC2G32 Dual 2-input OR gate Rev. 8 — 10 November 2010 Product data sheet 1. General description The 74LVC2G32 provides a 2-input OR gate function. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in a mixed 3.3 V and 5 V environment.

74AUP2G241

Abstract: 74AUP2G241DC 74AUP2G241GT
Contextual Info: 74AUP2G241 Low-power dual buffer/line driver; 3-state Rev. 04 — 13 September 2010 Product data sheet 1. General description The 74AUP2G241 provides a dual non-inverting buffer/line driver with 3-state outputs. The 3-state outputs are controlled by the output enable inputs 1OE and 2OE. A HIGH

74LVC2G126

Abstract: 74LVC2G126DC 74LVC2G126DP 74LVC2G126GD 74LVC2G126GM 74LVC2G126GT
Contextual Info: 74LVC2G126 Dual bus buffer/line driver; 3-state Rev. 9 — 13 September 2010 Product data sheet 1. General description The 74LVC2G126 is a dual non-inverting buffer/line driver with 3-state outputs. Each 3-state output is controlled by an output enable input pin nOE . A LOW-level at pin nOE

74AVC2T45

Abstract: 74AVC2T45DC 74AVC2T45GT
Contextual Info: 74AVC2T45 Dual-bit, dual-supply voltage level translator/transceiver; 3-state Rev. 5 — 30 November 2010 Product data sheet 1. General description The 74AVC2T45 is a dual-bit, dual-supply transceiver that enables bidirectional level translation. It features two data input-output ports nA and nB , a direction control input

Contextual Info: 74LVC2G32 Dual 2-input OR gate Rev. 10 — 22 June 2012 Product data sheet 1. General description The 74LVC2G32 provides a 2-input OR gate function. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in a mixed 3.3 V and 5 V environment.

NTB0102

Abstract: NTS0102 JESD22-A114E NTB0102DP NTB0102GD NTB0102GF NTB0102GT NTB0102GU
Contextual Info: NTB0102 Dual supply translating transceiver; auto direction sensing; 3-state Rev. 1 — 22 September 2010 Product data sheet 1. General description The NTB0102 is a 2-bit, dual supply translating transceiver with auto direction sensing, that enables bidirectional voltage level translation. It features two data input-output ports

PCA9306

Abstract: PCA9517A JESD22-A114 JESD22-A115 PCA9306D PCA9306DC PCA9306DP PCA9306DP1 PCA9509
Contextual Info: PCA9306 Dual bidirectional I2C-bus and SMBus voltage-level translator Rev. 05 — 19 March 2010 Product data sheet 1. General description The PCA9306 is a dual bidirectional I2C-bus and SMBus voltage-level translator with an enable EN input, and is operational from 1.0 V to 3.6 V (Vref(1) and 1.8 V to 5.5 V

74lvc3g14

Abstract: 74LVC3G14DC 74LVC3G14DP 74LVC3G14GM 74LVC3G14GT
Contextual Info: 74LVC3G14 Triple inverting Schmitt trigger with 5 V tolerant input Rev. 8 — 19 August 2010 Product data sheet 1. General description The 74LVC3G14 provides three inverting buffers with Schmitt trigger action. The inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of

74LVC3G34

Abstract: 74LVC3G34DC 74LVC3G34DP 74LVC3G34GD 74LVC3G34GM 74LVC3G34GT
Contextual Info: 74LVC3G34 Triple buffer Rev. 8 — 2 September 2010 Product data sheet 1. General description The 74LVC3G34 provides three buffers. The inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of the 74LVC3G34 as a translator in a mixed 3.3 V and 5 V environment.

nxp marking code x5

Abstract: 74LVC2T45 74LVC2T45DC
Contextual Info: 74LVC2T45; 74LVCH2T45 Dual supply translating transceiver; 3-state Rev. 4 — 20 August 2010 Product data sheet 1. General description The 74LVC2T45; 74LVCH2T45 are dual bit, dual supply translating transceivers with 3-state outputs that enable bidirectional level translation. They feature two data

74LVC2G241

Abstract: 74LVC2G241DC 74LVC2G241DP 74LVC2G241GD 74LVC2G241GM 74LVC2G241GT
Contextual Info: 74LVC2G241 Dual buffer/line driver; 3-state Rev. 10 — 6 August 2010 Product data sheet 1. General description The 74LVC2G241 is a dual non-inverting buffer/line driver with 3-state outputs. The 3-state outputs are controlled by the output enable inputs 1OE and 2OE:

74AUP2G132GF

Abstract: 74AUP2G132DC 74AUP2G132GM 74AUP2G132GT
Contextual Info: 74AUP2G132 Low-power dual 2-input NAND Schmitt trigger Rev. 4 — 4 November 2010 Product data sheet 1. General description The 74AUP2G132 provides the dual 2-input NAND Schmitt trigger function which accept standard input signals. They are capable of transforming slowly changing input signals

74AUP1G885

Abstract: 74AUP1G885DC 74AUP1G885GT JESD78
Contextual Info: 74AUP1G885 Low-power dual function gate Rev. 6 — 21 October 2010 Product data sheet 1. General description The 74AUP1G885 provides two functions in one device. The output state of the outputs 1Y, 2Y is determined by the inputs (A, B and C). The output 1Y provides the Boolean

74AUP1G74

Abstract: 74AUP1G74DC 74AUP1G74GD 74AUP1G74GT
Contextual Info: 74AUP1G74 Low-power D-type flip-flop with set and reset; positive-edge trigger Rev. 5 — 26 July 2010 Product data sheet 1. General description The 74AUP1G74 provides a low-power, low-voltage single positive-edge triggered D-type flip-flop with individual data D , clock (CP), set (SD) and reset (RD) inputs and

74LVC2G02

Abstract: 74LVC2G02DC 74LVC2G02DP 74LVC2G02GD 74LVC2G02GM 74LVC2G02GT
Contextual Info: 74LVC2G02 Dual 2-input NOR gate Rev. 8 — 20 October 2010 Product data sheet 1. General description The 74LVC2G02 provides a 2-input NOR gate function. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in a mixed 3.3 V and 5 V environment.