slot machine block diagram vhdl
Abstract: MPCI32 vhdl code dma controller ,vhdl code for implementation of eeprom 32Bit verilog code for pci to pci bridge pci verilog code verilog code for EEPROM Controller
Contextual Info: Inventra MPCI32 Soft Core RTL IP 32bit 33/66MHz PCI Core w/Cardbus support PCI Bus / Cardbus D A T A S H E E T Major Product Features: • Fully compliant with PCI v2.2 specification PCI Core for Peripheral Apps. PCI Bus Interface Target Register Interface
|
Original
|
mpci3232bit33/66mhzpd-40100+7003-foslot machine block diagram vhdlvhdl code dma controllervhdl code for implementation of eepromverilog code for pci to pci bridgepci verilog codeverilog code for eeprom controller
|
PDF
|
RTL code for ethernet
Abstract: PE-MCXMAC gmii phy ethernet mac verilog testbench Soft Core RTL FIFO
Contextual Info: A-MCXFIF Inventra™ Soft Core RTL IP FIFO Memory Interface for the PE-MCXMAC™ PEMXCMAC Core A-MXCFIF Core Fabric I/F 32 AMCXTFIF_FAB Fabric Tx Module Generic Synchronous 2 port SRAM Model AMCXTFIF_SYS 32 D A T A S H E E T Major Product Features: GMII
|
Original
|
pd-59060001-fortl code for ethernetpe-mcxmac+3gmii phyethernet mac verilog testbenchsoft core rtl fifo
|
PDF
|
UTM RESISTOR
Abstract: MUSBHDRC MUSBHDRC USB2.0 High-Speed Dual-Role Controller verilog code for amba ahb bus verilog code for amba ahb master verilog code AMBA AHB UTM power RESISTOR verilog code for frame synchronization AMBA AHB bus protocol Mentor
Contextual Info: Soft Core RTL IP Inventra MUSBHDRC USB2.0 High-Speed Dual-Role Controller D A T A S Endpoint Control EP0 Control - Host EP0 Control - Function EP1 - 15 Control Combine Endpoints DMA Requests Transmit IN Host Transaction Scheduler Interrupt Control Interrupts
|
Original
|
30mhzpd-40136002-foutm resistor+9musbhdrcmusbhdrc usb2.0 high-speed dual-role controllerverilog code for amba ahb busverilog code for amba ahb masterverilog code amba ahbutm power resistorverilog code for frame synchronizationamba ahb bus protocolmentor
|
PDF
|
verilog code for UART baud rate generator
Abstract: 16550AF verilog code for baud rate generator vhdl code for 8 bit parity generator baud rate generator verilog code for "baud rate" generator address generator logic vhdl code baud rate generator vhdl verilog code for active filter M16550A
Contextual Info: Inventra M16550S Enhanced UART with FIFOs and Synchronous CPU I/F Soft Core RTL IP D A T A S H E E T RCLK RCLK_BAUD BRGE BAUD RATE GENERATOR BAUD Major Product Features: • Software compatible with the NS 16550AF device • Programmable word length, stop bits
|
Original
|
m16550s16550af16-bytemode795+11pd-40125002-foverilog code for uart baud rate generatorverilog code for baud rate generatorvhdl code for 8 bit parity generatorbaud rate generatorverilog code for "baud rate" generatoraddress generator logic vhdl codebaud rate generator vhdlverilog code for active filterm16550a
|
PDF
|
verilog code AMBA AHB
Abstract: MUSBFDRC verilog code for 16 bit ram 40113 Mentor ahb bridge dma controller VERILOG MUSBFSFC RTL 8192
Contextual Info: Inventra MUSBHSFC Soft Core RTL IP USB 2.0 High/Full-Speed Function Controller D DMA Requests Endpoint Control EP0 Control EP1 - 15 Control IN IN MCU Interface OUTIN Interrupt Control Packet Encode/Decode Rx Sync Packet Encode TxRx Macrocell Tx Sync HS Detect
|
Original
|
2000/dmapd-40113004-foverilog code amba ahb+8musbfdrcverilog code for 16 bit ram40113mentorahb bridgedma controller verilogmusbfsfcrtl 8192
|
PDF
|
MUSBFDRC
Abstract: verilog code for amba ahb bus Mentor inventra USB Full-Speed Dual-Role Controller "USB" peripheral
Contextual Info: Inventra MUSBFDRC USB Full-Speed Dual-Role Controller Soft Core RTL IP D A T A S H E E T Endpoint Control EP0 Control - Host EP0 Control - Function EP1 - 15 Control DMA Requests Transmit IN Receive IN Host Transaction Scheduler Combine Endpoints CPU Interface
|
Original
|
pd-40134005-fomusbfdrcverilog code for amba ahb bus+3mentorinventra usb full-speed dual-role controllerusb" peripheral
|
PDF
|
vhdl code for 8 bit ram
Abstract: MUSBFSFC vhdl synchronous bus
Contextual Info: Inventra MUSBLSFC USB 1.1 Low-Speed Function Controller Soft Core RTL IP D A T A S H E E T Endpoint Control EP0 Control EP1 - 2 Control IN IN OUTIN Combine Endpoints Major Product Features: MCU Interface Interrupt Control Interrupts EP Reg. Decoder Low-speed (1.5 Mbps) functions
|
Original
|
p1795pd-40103002-fovhdl code for 8 bit ram+2musbfsfcvhdl synchronous bus
|
PDF
|
alcatel 1603
Contextual Info: Inventra Soft Core RTL IP PE-SMII Serial MII I/F for PE-MACMII™ Ethernet MAC Tx Data Tx Data PEMCS Tx Status PETFUN PESMII SMII PHY Rx Data Serial MII Interface Module Rx Data Rx Status A T A S H E E T Major Product Features: PE-MACMII Core HOST D • Works with Alcatel PE-MACMII
|
Original
|
10/100mbps125mhzmodu795pd-59016+2001-foalcatel 1603
|
PDF
|
82c250
Abstract: MCAN2 40107 BOSCH CAN vhdl bosch can 2.0B BOSCH CAN CONTROLLER vhdl BOSCH CAN Bosch SJA1000 82C250 CAN Driver
Contextual Info: Soft Core RTL IP Inventra MCAN2 CAN 2.0 Network Controller D Transmit Buffer A T A S H E E T Major Product Features: WDATA[7:0] • Supports full CAN 2.0 – both 2.0A (equivalent to CAN 1.2) and 2.0B RDATA[7:0] CPU Interface 64 byte • Supports 11-bit & 29-bit identifiers
|
Original
|
11-bit29-bit125kbaud64-byte+13listen-only795pd-40107001-fo82c250mcan240107bosch can vhdlbosch can 2.0bbosch can controller vhdlbosch canboschsja100082c250 can driver
|
PDF
|
RMII PHY
Abstract: 59014 alcatel 1603 rMII verilog 59014 transistor RMII Specification
Contextual Info: Inventra Soft Core RTL IP PE-RMII RMII I/F for PE-MACMII™ 10/100 Ethernet MAC Tx Data Tx Data PEMCS Tx Status PETFUN PERMII Reduced MII Interface Module Rx Data Rx Status Control PECLKRST RMII PHY Tx Control T A S H E E T PEMIIM • Works with Alcatel PE-MACMII
|
Original
|
10/100mbps50mhzpd-59014001-fo+6rmii phy59014alcatel 1603rmii verilog59014 transistorrmii specification
|
PDF
|
pci core
Abstract: Soft Core RTL FIFO synchronous fifo design in verilog
Contextual Info: PCI Peripheral Core PCI ADOUT Register Core Block Diagram PCI Parity Multiplexer Register Master Write FIFO PCI Bus Register Master Read FIFO Master State Machine/ DMA Register Master Request FIFO Output Mux Application Interface PCI I/O Cells ▼ Configuration
|
Original
|
32-bit64-bitasic-fs-20827-10/99pci core+2soft core rtl fifosynchronous fifo design in verilog
|
PDF
|
Soft Core RTL USB
Abstract: microelectronics ASIC USB 2.0 coach 12 Shenzhen State Microelectronics UDC20 RTL 604 GDS VCI
Contextual Info: Standard Bus IP: High Speed USB 2.0 Device Controller Fujitsu Macro F_USB20LP LINK PHY CPU Fujitsu USB 2.0 device controller is a synthesizable core suitable for different process. Corresponding physical interface in 0.18um and 0.11um technology supporting high and full speed operation
|
Original
|
usb20lpsoft core rtl usbmicroelectronicsasic usb 2.0+5coach 12shenzhen state microelectronicsudc20rtl 604gds vci
|
PDF
|
RTL 204 601
Abstract: 400x240 conector RJ catalog ShMM-1500R leon3 VME64 alma 8051s CZ80CPU A24D16 RT MIL-STD-1553B ACTEL FPGA
Contextual Info: Solutions and IP Catalog Improve Time-to-Market and Reduce Risk March 2010 Table of Contents Introduction 3 Power Management Solutions Mixed-Signal Power Manager MPM 4 System Management Solutions Pigeon Point Systems 5 Motor Control Solutions 6 Display Solutions
|
Original
|
core8051score10/100core429core1553brm+14core1553brtcore1553brt-ebrcore1553bbccoreaes128rtl 204 601400x240conector rj catalogshmm-1500rleon3vme64 alma8051scz80cpua24d16rt mil-std-1553b actel fpga
|
PDF
|
verilog code for slave SPI with FPGA
Abstract: EP1C3T100C8 vhdl spi interface vhdl spi bus VHDL code for slave SPI with FPGA "Serial peripheral interface" vhdl synchronous bus vhdl code for 8 bit shift register verilog code for 64 32 bit register
Contextual Info: SPI_MS Serial Peripheral Interface Master/Slave Altera Core The Serial Peripheral Interface SPI allows high-speed synchronous serial data transfers between microprocessors, microcontrollers and peripheral devices. The SPI_MS core implements the Serial Peripheral Interface, which can operate either
|
Original
|
verilog code for slave spi with fpgaep1c3t100c8vhdl spi interfacevhdl spi bus+5vhdl code for slave spi with fpgaserial peripheral interfacevhdl synchronous busvhdl code for 8 bit shift registerverilog code for 64 32 bit register
|
PDF
|
|
|
verilog code for slave SPI with FPGA
Abstract: vhdl spi interface VHDL code for slave SPI with FPGA
Contextual Info: SPI_MS Serial Peripheral Interface Master/Slave Core The Serial Peripheral Interface SPI allows high-speed synchronous serial data transfers between microprocessors, microcontrollers and peripheral devices. The SPI_MS core implements the Serial Peripheral Interface, which can operate either
|
Original
|
verilog code for slave spi with fpgavhdl spi interfacevhdl code for slave spi with fpga |
PDF
|
100-BASE-FX
Abstract: 10BASE5 10Base-2 802.3 fx
Contextual Info: 10/100 Mbps Ethernet MAC Core MAC Tx FIFO Transmit Block Core Block Diagram DII Flow Control Address Recognition Logic ▼ CSR Interface Command and Status Registers Receive Block MAC Rx FIFO Features • DMA Independent Interface DII for generic interface to
|
Original
|
asic-fs-20814-10/99100-base-fx10base510base-2+1802.3 fx
|
PDF
|
verilog code for apb
Abstract: verilog code for amba apb bus AMBA APB bus spdif input processor bit stream verilog code for amba apb master verilog code for transmitter IEC-60958 spdif input spdif input processor FIFO amba apb
Contextual Info: Conforms to the IEC 60958 International Standard Programmable: supports both Receiver and Transmitter modes SPDIF-APB Data mode capabilities: Digital Audio Interface Core o Supports sample rates from 3kHz to 192kHz with 98MHz SPDIF system clock o 20/24 bits per sample
|
Original
|
192khz98mhzverilog code for apbverilog code for amba apb bus+8amba apb busspdif input processor bit streamverilog code for amba apb masterverilog code for transmitteriec-60958spdif inputspdif input processor fifoamba apb
|
PDF
|
16550A serial communication
Abstract: 16550A UART texas instruments datasheet of 16450 UART 16450 UART 16550A UART H16550S
Contextual Info: Capable of running all existing 16450 and 16550a software H16550S Fully Synchronous design. All inputs and outputs are based on rising edge of clock UART with FIFOs and Synchronous CPU Interface Core In FIFO mode, the transmitter and receiver are each buffered
|
Original
|
16550ah16550s16450-compatible16550compatible+516550a serial communication16550a uart texas instrumentsdatasheet of 16450 uart16450 uart16550a uart
|
PDF
|
16550A serial communication
Abstract: 16450 16550A H16550S LFX125EB-3 17e7
Contextual Info: H16550S UART with FIFOs and Synchronous CPU Interface Core The H16550S is a standard UART providing 100% software compatibility with the popular Texas Instruments 16550 device. It performs serial-to-parallel conversion on data originating from modems or other serial devices, and performs parallel-to-serial
|
Original
|
h16550s16450-compatible16550compatible16550a serial communication+41645016550alfx125eb-317e7
|
PDF
|
verilog code for phy interface
Abstract: 64Byte UDC20 usb interface engine UDC-20
Contextual Info: USB 2.0 Device Controller Macro Fujitsu Macro F_USB20LP_03 LINK PHY CPU RAM ROM Local CPU Bus 32bit Control Status Register Interrupt Local Bus Interface Internal Bus UTMI Protocol Engine (UDC-20) PHY USB End-Point FIFO ▲ Features • Full compliance with USB 2.0 Device Controller
|
Original
|
usb20lp32bitudc-20480mbps+612mbpsasic-fs-20919-3/2002verilog code for phy interface64byteudc20usb interface engine
|
PDF
|
PCA82C250T
Abstract: Bosch bosch can 2.0B LFX1200B-5
Contextual Info: Implementation of the Basic CAN specification CAN Bus Controller Core No generated Overload Frames Receiving and transmitting of both identifiers CAN specification 2.0B Programmable data rate up to 1 mbps Programmable baud rate prescaler (up to 1/30) Application specific interface to
|
Original
|
pca82c250tlfec20e-5lfxp2-17e-7lcmxo2280c-5+6lfxp10-c-5lfe2-50-7lfsc3ga25-7boschbosch can 2.0blfx1200b-5
|
PDF
|
Soft Core RTL USB
Abstract: "Single-Port RAM" USB 3.0 device USB Controller USB 1.0 specification requirements usb 3.0 LFPS verilog code for amba ahb master "USB" peripheral
Contextual Info: 32-bit OCP Slave interface implemented as a basic microprocessor interface USB3-DEV USB 3.0 SuperSpeed Device Controller IP Core This IP core implements a device controller that conforms to the USB 3.0 SuperSpeed specification. SuperSpeed 3.0 USB enables data transfers up to 5 Gbps while also reducing power
|
Original
|
32-bitsoft core rtl usbsingle-port ramusb 3.0 device+5usb controller usb 1.0specification requirements usb 3.0lfpsverilog code for amba ahb masterusb" peripheral
|
PDF
|
CUSB2
Abstract: ISP1501
Contextual Info: Full compliance with the USB 2.0 specification CUSB2 USB 2.0 Device Controller Core Control endpoint 0 — fixed 64 Bytes size Configurable for up to 15 IN and 15 OUT endpoints Configurable/programmable number and size of endpoints Configurable/programmable
|
Original
|
lfx500c-4cusb2isp1501 |
PDF
|
ISERDES2
Abstract: spartan hdmi oserdes2 oserdes2 DDR spartan6 TMDS33 HDMI verilog code Spartan-6 FPGA DCM_CLKGEN XAPP495 tmds fpga XAPP460
Contextual Info: Application Note: Spartan-6 Family Implementing a TMDS Video Interface in the Spartan-6 FPGA Author: Bob Feng XAPP495 v1.0 December 13, 2010 Summary Transition Minimized Differential Signaling (TMDS) is a standard used for transmitting video data over the Digital Visual Interface (DVI) and High-Definition Multimedia Interface (HDMI).
|
Original
|
xapp495iserdes2spartan hdmioserdes2+6oserdes2 ddr spartan6tmds33hdmi verilog codespartan-6 fpga dcm_clkgentmds fpgaxapp460
|
PDF
|
