SN54LV74 Search Results

74lv74a

Abstract: LV74A A115-A C101 SN54LV74A SN74LV74A SN74LV74AD
Contextual Info: SN54LV74A, SN74LV74A DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS SCLS381F – AUGUST 1997 – REVISED JANUARY 2001 D D D D SN54LV74A . . . J OR W PACKAGE SN74LV74A . . . D, DB, DGV, NS, OR PW PACKAGE TOP VIEW 2-V to 5.5-V VCC Operation Typical VOLP (Output Ground Bounce)

Contextual Info: SN54LV74, SN74LV74 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS SCLS189C – FEBRUARY 1993 – REVISED APRIL 1996 D D D D D EPIC  Enhanced-Performance Implanted CMOS 2-µ Process Typical VOLP (Output Ground Bounce) < 0.8 V at VCC, TA = 25°C Typical VOHV (Output VOH Undershoot)

Contextual Info: SN54LV74A, SN74LV74A DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS SCLS381L − AUGUST 1997 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 8.5 ns at 5 V D Typical VOLP Output Ground Bounce SN54LV74A . . . J OR W PACKAGE SN74LV74A . . . D, DB, DGV, NS,

A115-A

Abstract: C101 SN54LV74A SN74LV74A SN74LV74ARGYR
Contextual Info: SN54LV74A, SN74LV74A DUAL POSITIVEĆEDGEĆTRIGGERED DĆTYPE FLIPĆFLOPS SCLS381L − AUGUST 1997 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 8.5 ns at 5 V D Typical VOLP Output Ground Bounce SN54LV74A . . . J OR W PACKAGE SN74LV74A . . . D, DB, DGV, NS,

Contextual Info: SN54LV74A, SN74LV74A DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS SCLS381I – AUGUST 1997 – REVISED OCTOBER 2002 SN54LV74A . . . J OR W PACKAGE SN74LV74A . . . D, DB, DGV, NS, OR PW PACKAGE TOP VIEW 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 2CLR 2D 2CLK 2PRE

Contextual Info: SN54LV74, SN74LV74 DUAL POSITIVEĆEDGEĆTRIGGERED DĆTYPE FLIPĆFLOPS SCLS189C − FEBRUARY 1993 − REVISED APRIL 1996 D EPIC  Enhanced-Performance Implanted D D D D CMOS 2-µ Process Typical VOLP (Output Ground Bounce) < 0.8 V at VCC, TA = 25°C Typical VOHV (Output VOH Undershoot)

Contextual Info: SN54LV74A, SN74LV74A DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS SCLS381L − AUGUST 1997 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 8.5 ns at 5 V D Typical VOLP Output Ground Bounce SN54LV74A . . . J OR W PACKAGE SN74LV74A . . . D, DB, DGV, NS,

A115-A

Abstract: C101 SN54LV74A SN74LV74A SN74LV74ARGYR 2525Q
Contextual Info: SN54LV74A, SN74LV74A DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS SCLS381I – AUGUST 1997 – REVISED OCTOBER 2002 SN54LV74A . . . J OR W PACKAGE SN74LV74A . . . D, DB, DGV, NS, OR PW PACKAGE TOP VIEW 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 2CLR 2D 2CLK 2PRE

Contextual Info: SN54LV74A, SN74LV74A DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS SCLS381I – AUGUST 1997 – REVISED OCTOBER 2002 SN54LV74A . . . J OR W PACKAGE SN74LV74A . . . D, DB, DGV, NS, OR PW PACKAGE TOP VIEW 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 2CLR 2D 2CLK 2PRE

Contextual Info: SN54LV74, SN74LV74 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS SC LS 189C - FEBRUARY 1993 - REVISED APRIL 1986 EPIC Enhanced-Performance Implanted CMOS 2-|i Process Typical V q l p (Output Ground Bounce) < 0.8 V at VCc. Ta = 25°C Typical V q h v (Output Voh Undershoot)

A115-A

Abstract: C101 SN54LV74A SN74LV74A SN74LV74ARGYR LV74a
Contextual Info: SN54LV74A, SN74LV74A DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS SCLS381J – AUGUST 1997 – REVISED AUGUST 2003 SN54LV74A . . . J OR W PACKAGE SN74LV74A . . . D, DB, DGV, NS, OR PW PACKAGE TOP VIEW 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 2CLR 2D 2CLK 2PRE

A115-A

Abstract: C101 SN54LV74A SN74LV74A SN74LV74ARGYR 74LV74
Contextual Info: SN54LV74A, SN74LV74A DUAL POSITIVEĆEDGEĆTRIGGERED DĆTYPE FLIPĆFLOPS SCLS381L − AUGUST 1997 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 8.5 ns at 5 V D Typical VOLP Output Ground Bounce SN54LV74A . . . J OR W PACKAGE SN74LV74A . . . D, DB, DGV, NS,

Contextual Info: SN54LV74A, SN74LV74A DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS SCLS381 A -A U G U S T 1997-R E V IS E D OCTOBER 1997 EPIC Enhanced-Performance Implanted CMOS Process SN54LV74A . . J OR W PACKAGE SN74LV74A . . . D, DB, NS, OR PW PACKAGE (TOP VIEW)

Contextual Info: SN54LV74A, SN74LV74A DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS SCLS381L − AUGUST 1997 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 8.5 ns at 5 V D Typical VOLP Output Ground Bounce SN54LV74A . . . J OR W PACKAGE SN74LV74A . . . D, DB, DGV, NS,

A115-A

Abstract: C101 SN54LV74A SN74LV74A SN74LV74ARGYR
Contextual Info: SN54LV74A, SN74LV74A DUAL POSITIVEĆEDGEĆTRIGGERED DĆTYPE FLIPĆFLOPS SCLS381L − AUGUST 1997 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 8.5 ns at 5 V D Typical VOLP Output Ground Bounce SN54LV74A . . . J OR W PACKAGE SN74LV74A . . . D, DB, DGV, NS,

Contextual Info: SN54LV74A, SN74LV74A DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS SCLS381D – AUGUST 1997 – REVISED JUNE 1998 D D D D description These dual positive-edge-triggered D-type flip-flops are designed for 2-V to 5.5-V VCC operation. A low level at the preset PRE or clear (CLR)

74LV74

Contextual Info: SN54LV74A, SN74LV74A DUAL POSITIVEĆEDGEĆTRIGGERED DĆTYPE FLIPĆFLOPS SCLS381L − AUGUST 1997 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 8.5 ns at 5 V D Typical VOLP Output Ground Bounce SN54LV74A . . . J OR W PACKAGE SN74LV74A . . . D, DB, DGV, NS,

SN54LV74A

Abstract: SN74LV74A 122d
Contextual Info: SN54LV74A, SN74LV74A DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS SCLS381E – AUGUST 1997 – REVISED MAY 2000 D D D D D D D EPIC  Enhanced-Performance Implanted CMOS Process Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C Typical VOHV (Output VOH Undershoot)

Contextual Info: SN54LV74A, SN74LV74A DUAL POSITIVEĆEDGEĆTRIGGERED DĆTYPE FLIPĆFLOPS SCLS381L − AUGUST 1997 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 8.5 ns at 5 V D Typical VOLP Output Ground Bounce SN54LV74A . . . J OR W PACKAGE SN74LV74A . . . D, DB, DGV, NS,

Contextual Info: SN54LV74, SN74LV74 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS SCLS189C – FEBRUARY 1993 – REVISED APRIL 1996 D D D D D EPIC  Enhanced-Performance Implanted CMOS 2-µ Process Typical VOLP (Output Ground Bounce) < 0.8 V at VCC, TA = 25°C Typical VOHV (Output VOH Undershoot)

Contextual Info: SN54LV74A, SN74LV74A DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS SCLS381J – AUGUST 1997 – REVISED AUGUST 2003 SN54LV74A . . . J OR W PACKAGE SN74LV74A . . . D, DB, DGV, NS, OR PW PACKAGE TOP VIEW 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 2CLR 2D 2CLK 2PRE

SN54LV74

Abstract: SN74LV74
Contextual Info: SN54LV74, SN74LV74 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS SCLS189C – FEBRUARY 1993 – REVISED APRIL 1996 D D D D D EPIC  Enhanced-Performance Implanted CMOS 2-µ Process Typical VOLP (Output Ground Bounce) < 0.8 V at VCC, TA = 25°C Typical VOHV (Output VOH Undershoot)

74LV74

Contextual Info: SN54LV74A, SN74LV74A DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS SCLS381L − AUGUST 1997 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 8.5 ns at 5 V D Typical VOLP Output Ground Bounce SN54LV74A . . . J OR W PACKAGE SN74LV74A . . . D, DB, DGV, NS,

SN54LV74A

Abstract: SN74LV74A SN74LV74ARGYR A115-A C101
Contextual Info: SN54LV74A, SN74LV74A DUAL POSITIVEĆEDGEĆTRIGGERED DĆTYPE FLIPĆFLOPS SCLS381K − AUGUST 1997 − REVISED DECEMBER 2004 D 2-V to 5.5-V VCC Operation D Max tpd of 8.5 ns at 5 V D Typical VOLP Output Ground Bounce SN54LV74A . . . J OR W PACKAGE SN74LV74A . . . D, DB, DGV, NS,