SN74LV74 Search Results

74lv74a

Abstract: LV74A A115-A C101 SN54LV74A SN74LV74A SN74LV74AD
Contextual Info: SN54LV74A, SN74LV74A DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS SCLS381F – AUGUST 1997 – REVISED JANUARY 2001 D D D D SN54LV74A . . . J OR W PACKAGE SN74LV74A . . . D, DB, DGV, NS, OR PW PACKAGE TOP VIEW 2-V to 5.5-V VCC Operation Typical VOLP (Output Ground Bounce)

Contextual Info: SN74LV74A-EP DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS www.ti.com SCLS696 – JANUARY 2006 FEATURES • • • • • • • • • • • 1 Controlled Baseline – One Assembly/Test Site, One Fabrication Site Extended Temperature Performance of– 55°C

Contextual Info: SN74LV74A-EP DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS www.ti.com SCLS696 – JANUARY 2006 FEATURES • • • • • • • • • • • 1 Controlled Baseline – One Assembly/Test Site, One Fabrication Site Extended Temperature Performance of– 55°C

Contextual Info: SN74LV74A-EP DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS www.ti.com SCLS696 – JANUARY 2006 FEATURES • • • • • • • • • • • 1 Controlled Baseline – One Assembly/Test Site, One Fabrication Site Extended Temperature Performance of– 55°C

Contextual Info: SN74LV74A-EP DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS www.ti.com SCLS696 – JANUARY 2006 FEATURES • • • • • • • • • • • 1 Controlled Baseline – One Assembly/Test Site, One Fabrication Site Extended Temperature Performance of– 55°C

Contextual Info: SN54LV74, SN74LV74 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS SCLS189C – FEBRUARY 1993 – REVISED APRIL 1996 D D D D D EPIC  Enhanced-Performance Implanted CMOS 2-µ Process Typical VOLP (Output Ground Bounce) < 0.8 V at VCC, TA = 25°C Typical VOHV (Output VOH Undershoot)

Contextual Info: SN54LV74A, SN74LV74A DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS SCLS381L − AUGUST 1997 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 8.5 ns at 5 V D Typical VOLP Output Ground Bounce SN54LV74A . . . J OR W PACKAGE SN74LV74A . . . D, DB, DGV, NS,

A115-A

Abstract: C101 SN54LV74A SN74LV74A SN74LV74ARGYR
Contextual Info: SN54LV74A, SN74LV74A DUAL POSITIVEĆEDGEĆTRIGGERED DĆTYPE FLIPĆFLOPS SCLS381L − AUGUST 1997 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 8.5 ns at 5 V D Typical VOLP Output Ground Bounce SN54LV74A . . . J OR W PACKAGE SN74LV74A . . . D, DB, DGV, NS,

Contextual Info: SN54LV74A, SN74LV74A DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS SCLS381I – AUGUST 1997 – REVISED OCTOBER 2002 SN54LV74A . . . J OR W PACKAGE SN74LV74A . . . D, DB, DGV, NS, OR PW PACKAGE TOP VIEW 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 2CLR 2D 2CLK 2PRE

Contextual Info: SN54LV74, SN74LV74 DUAL POSITIVEĆEDGEĆTRIGGERED DĆTYPE FLIPĆFLOPS SCLS189C − FEBRUARY 1993 − REVISED APRIL 1996 D EPIC  Enhanced-Performance Implanted D D D D CMOS 2-µ Process Typical VOLP (Output Ground Bounce) < 0.8 V at VCC, TA = 25°C Typical VOHV (Output VOH Undershoot)

Contextual Info: SN74LV74AĆQ1 DUAL POSITIVEĆEDGEĆTRIGGERED DĆTYPE FLIPĆFLOP SCLS556A − DECEMBER 2003 − REVISED MAY 2004 D Qualification in Accordance With D OR PW PACKAGE TOP VIEW AEC-Q100† D Qualified for Automotive Applications D Customer-Specific Configuration Control

Contextual Info: SN74LV74A-EP DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS www.ti.com SCLS696 – JANUARY 2006 FEATURES • • • • • • • • • • • 1 Controlled Baseline – One Assembly/Test Site, One Fabrication Site Extended Temperature Performance of– 55°C

Contextual Info: SN74LV74A-EP DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS www.ti.com SCLS696 – JANUARY 2006 FEATURES • • • • • • • • • • • 1 Controlled Baseline – One Assembly/Test Site, One Fabrication Site Extended Temperature Performance of– 55°C

Contextual Info: SN74LV74A-EP DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS www.ti.com SCLS696 – JANUARY 2006 FEATURES • • • • • • • • • • • 1 Controlled Baseline – One Assembly/Test Site, One Fabrication Site Extended Temperature Performance of– 55°C

A115-A

Abstract: C101 SN54LV74A SN74LV74A SN74LV74ARGYR 2525Q
Contextual Info: SN54LV74A, SN74LV74A DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS SCLS381I – AUGUST 1997 – REVISED OCTOBER 2002 SN54LV74A . . . J OR W PACKAGE SN74LV74A . . . D, DB, DGV, NS, OR PW PACKAGE TOP VIEW 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 2CLR 2D 2CLK 2PRE

Contextual Info: SN74LV74A-EP DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS www.ti.com SCLS696 – JANUARY 2006 FEATURES • • • • • • • • • • • 1 Controlled Baseline – One Assembly/Test Site, One Fabrication Site Extended Temperature Performance of– 55°C

Contextual Info: SN74LV74A-EP DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS www.ti.com SCLS696 – JANUARY 2006 FEATURES • • • • • • • • • • • 1 Controlled Baseline – One Assembly/Test Site, One Fabrication Site Extended Temperature Performance of– 55°C

Contextual Info: SN74LV74A-EP DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS www.ti.com SCLS696 – JANUARY 2006 FEATURES • • • • • • • • • • • 1 Controlled Baseline – One Assembly/Test Site, One Fabrication Site Extended Temperature Performance of– 55°C

Contextual Info: SN54LV74A, SN74LV74A DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS SCLS381I – AUGUST 1997 – REVISED OCTOBER 2002 SN54LV74A . . . J OR W PACKAGE SN74LV74A . . . D, DB, DGV, NS, OR PW PACKAGE TOP VIEW 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 2CLR 2D 2CLK 2PRE

Contextual Info: SN54LV74, SN74LV74 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS SC LS 189C - FEBRUARY 1993 - REVISED APRIL 1986 EPIC Enhanced-Performance Implanted CMOS 2-|i Process Typical V q l p (Output Ground Bounce) < 0.8 V at VCc. Ta = 25°C Typical V q h v (Output Voh Undershoot)

37Ti

Abstract: SN74LV74
Contextual Info: SN74LV74 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP SCLS189A - FEBRUARY 19 9 3 - REVISED JULY 1995 D, DB, OR PW PACKAGE c ro p VIEW EPIC Enhanced-Performance Implanted CMOS) 2-ii Process Typical V o l p (Output Ground Bounce) < 0.8 V at VCc = 3.3 V, TA = 25°C

A115-A

Abstract: C101 SN54LV74A SN74LV74A SN74LV74ARGYR LV74a
Contextual Info: SN54LV74A, SN74LV74A DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS SCLS381J – AUGUST 1997 – REVISED AUGUST 2003 SN54LV74A . . . J OR W PACKAGE SN74LV74A . . . D, DB, DGV, NS, OR PW PACKAGE TOP VIEW 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 2CLR 2D 2CLK 2PRE

A115-A

Abstract: C101 SN54LV74A SN74LV74A SN74LV74ARGYR 74LV74
Contextual Info: SN54LV74A, SN74LV74A DUAL POSITIVEĆEDGEĆTRIGGERED DĆTYPE FLIPĆFLOPS SCLS381L − AUGUST 1997 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 8.5 ns at 5 V D Typical VOLP Output Ground Bounce SN54LV74A . . . J OR W PACKAGE SN74LV74A . . . D, DB, DGV, NS,

Contextual Info: SN74LV74A-EP DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS www.ti.com SCLS696 – JANUARY 2006 FEATURES • • • • • • • • • • • 1 Controlled Baseline – One Assembly/Test Site, One Fabrication Site Extended Temperature Performance of– 55°C