SN54HC1 Search Results

54HC154

Contextual Info: SN54HC154, SN74HC154 LINE TO 16 LINE DECODERS/DEMULTIPLEXERS D 2 6 8 4 , DECEMBER 1 9 8 2 -R E V IS E D SEPTEMBER 1987 • Decodes 4 Binary-Coded Inputs into One of 16 Mutually Exclusive Outputs • Performs the Demultiplexing Function by Distributing Data From One Input to Any

Contextual Info: SN54HC132, SN74HC132 QUADRUPLE POSITIVE-NAND GATES WITH SCHMITT-TRIGGER INPUTS SCLS034B - DECEMBER 1982 - REVISED JANUARY 1996 • • • • • Operation From Very Slow Input Transitions Temperature-Compensated Threshold Levels High Noise Immunity Same Pinouts as ’HCOO

54HC112

Contextual Info: SN54HC112, SN74HC112 DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET 02684, DECEMBER 1982-REVISED SEPTEMBER 1987 SN54HC112 . . . J PACKAGE SN74HC112 . . . D OR N PACKAGE TOP VIEW ] 1CLK C 1 O l 6 H V CC i k C 2 15 3 1CLR 14 H 2CLR u [ 3

SM74HC125

Abstract: HC12S 8112G
Contextual Info: SN54HC125, SN54HC126 SN74HC12S, SN74HC126 QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS D2804, M A R C H 1 9 8 4 - R E V IS E D JU N E 1989 SN54HC125. SN54HC126 . SN74HC125, S N 7 4 H C 1 26 . 'High-Current 3-State Outputs Interface Directly with System Bus or Can Drive Up

Contextual Info: SN54HC139, SN74HC139 DUAL 2 LINE TO 4-LINE DECODERS/DEMULTIPLEXERS D 2 6 8 4 , DECEMBER 1 9 8 2 -R E V IS E D SEPTEMBER 1987 D esigned S pecifically for H igh-Speed S N 5 4 H C 1 3 9 . . . J PACKAGE S N 7 4 H C 1 3 9 . . . O W OR N PACKAGE M e m o ry D ecoders and D ata Transm ission

SCLS11

Contextual Info: SN54HC151, SN74HC151 8-LINE TO 1-LINE DATA SELECTORS/MULTIPLEXERS SCLS11 OB-DECEMBER 1982 - JULY 1996 8-Line to 1-Llne Multiplexers Can Perform as: - Boolean Function Generators - Parallel-to-Serlal Converters - Data Source Selectors Package Options Include Plastic

Contextual Info: SN54HC193, SN74HC193 4-BIT SYNCHRONOUS UP/DOWN COUNTERS DUAL CLOCK WITH CLEAR SCLS122B – DECEMBER 1982 – REVISED MAY 1997 D D D D D Look-Ahead Circuitry Enhances Cascaded Counters Fully Synchronous in Count Modes Parallel Asynchronous Load for Modulo-N

Contextual Info: SN54HC165, SN74HC165 8-BIT PARALLEL-LOAD SHIFT REGISTERS SCLS116C – DECEMBER 1982 – REVISED MAY 1997 D D D D D Complementary Outputs Direct Overriding Load Data Inputs Gated Clock Inputs Parallel-to-Serial Data Conversion Package Options Include Plastic

SN74HC132

Abstract: HC00 HC132 SN54HC132 SN74HC132D SN74HC132DR SN74HC132DT SN74HC132N SN74HC132NSR
Contextual Info: SN54HC132, SN74HC132 QUADRUPLE POSITIVEĆNAND GATES WITH SCHMITTĆTRIGGER INPUTS SCLS034F − DECEMBER 1982 − REVISED NOVEMBER 2004 D D D Wide Operating Voltage Range of 2 V to 6 V Outputs Can Drive Up To 10 LSTTL Loads Low Power Consumption, 20-µA Max ICC

SN74HC138D

Abstract: SN74HC138DR SN74HC138DT HC138 SN54HC138 SN74HC138 SN74HC138DBR SN74HC138N SN74HC138NSR SN54HC138J
Contextual Info: SN54HC138, SN74HC138 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS SCLS107E − DECEMBER 1982 − REVISED SEPTEMBER 2003 D Targeted Specifically for High-Speed D D D D D D D Memory Decoders and Data-Transmission Systems Wide Operating Voltage Range of 2 V to 6 V

HC139

Abstract: SN54HC139 SN74HC139 SN74HC139D SN74HC139DBR SN74HC139DR SN74HC139DT SN74HC139N SN74HC139NSR
Contextual Info: SN54HC139, SN74HC139 DUAL 2ĆLINE TO 4ĆLINE DECODERS/DEMULTIPLEXERS SCLS108D − DECEMBER 1982 − REVISED SEPTEMBER 2003 D Targeted Specifically for High-Speed D D D D D D D SN54HC139 . . . J OR W PACKAGE SN74HC139 . . . D, DB, N, NS, OR PW PACKAGE TOP VIEW

SN54HC126

Abstract: SN74HC126 SN74HC126D SN74HC126DBR SN74HC126DR SN74HC126N SN74HC126NSR SN74HC126PW SN74HC126PWR
Contextual Info: SN54HC126, SN74HC126 QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS SCLS103D – MARCH 1984 – REVISED DECEMBER 2002 D D D D D D Wide Operating Voltage Range of 2 V to 6 V High-Current 3-State Outputs Interface Directly With System Bus or Can Drive Up To 15 LSTTL Loads

Contextual Info: SN54HC126, SN74HC126 QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS SCLS103E – MARCH 1984 – REVISED JULY 2003 D D D Wide Operating Voltage Range of 2 V to 6 V High-Current 3-State Outputs Interface Directly With System Bus or Can Drive Up To 15 LSTTL Loads

Contextual Info: SN54HC193, SN74HC193 4ĆBIT SYNCHRONOUS UP/DOWN COUNTERS DUAL CLOCK WITH CLEAR SCLS122D − DECEMBER 1982 − REVISED OCTOBER 2003 D D D D D D Wide Operating Voltage Range of 2 V to 6 V Outputs Can Drive Up To 10 LSTTL Loads Low Power Consumption, 80-µA Max ICC

Contextual Info: SN54HC138, SN74HC138 3ĆLINE TO 8ĆLINE DECODERS/DEMULTIPLEXERS SCLS107E − DECEMBER 1982 − REVISED SEPTEMBER 2003 D Targeted Specifically for High-Speed D D D D D D D Memory Decoders and Data-Transmission Systems Wide Operating Voltage Range of 2 V to 6 V

Contextual Info: SN54HC165, SN74HC165 8ĆBIT PARALLELĆLOAD SHIFT REGISTERS SCLS116E − DECEMBER 1982 − REVISED SEPTEMBER 2003 D D D D D Wide Operating Voltage Range of 2 V to 6 V Outputs Can Drive Up To 10 LSTTL Loads Low Power Consumption, 80-µA Max ICC Typical tpd = 13 ns

HC11

Abstract: SN54HC11 SN74HC11 SN74HC11D SN74HC11DBR SN74HC11DR SN74HC11N SN74HC11NSR SN74HC11PW
Contextual Info: SN54HC11, SN74HC11 TRIPLE 3ĆINPUT POSITIVEĆAND GATES SCLS084C – DECEMBER 1982 – REVISED NOVEMBER 2002 D Wide Operating Voltage Range of 2 V to 6 V D Outputs Can Drive Up to 10 LSTTL Loads D Low Power Consumption, 20-µA Max ICC D Typical tpd = 8 ns D ±4-mA Output Drive at 5 V

HC161

Abstract: SN54HC161 SN74HC161 SN74HC161D SN74HC161DR SN74HC161N SN74HC161NSR SN74HC161PWR SNJ54HC161J
Contextual Info: SN54HC161, SN74HC161 4ĆBIT SYNCHRONOUS BINARY COUNTERS SCLS297B – JANUARY 1996 – REVISED DECEMBER 2002 D D D D D D D D D D SN54HC161 . . . J OR W PACKAGE SN74HC161 . . . D, N, NS, OR PW PACKAGE TOP VIEW Wide Operating Voltage Range of 2 V to 6 V Outputs Can Drive Up To 10 LSTTL Loads

SN74HC125

Abstract: SN54HC125 K911
Contextual Info: SN54HC125, SN74HC125 QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS S C LS104A - M ARCH 1984 - R EV IS E D JANUARY 1996 High-Current 3-State Outputs Interface Directly With System Bus or Can Drive up to 15 LSTTL Loads SN54HC125 . . . J OR W PACKAGE SN74HC125 . . . D, DB, OR N PACKAGE

HC109

Abstract: SN54HC109 SN74HC109 SN74HC109D SN74HC109DR SN74HC109DT SN74HC109N SN74HC109NSR SNJ54HC109J SNJ54HC109W
Contextual Info: SN54HC109, SN74HC109 DUAL JĆK POSITIVEĆEDGEĆTRIGGERED FLIPĆFLOPS WITH CLEAR AND PRESET SCLS470A − MARCH 2003 − REVISED OCTOBER 2003 D Wide Operating Voltage Range of 2 V to 6 V D Low Input Current of 1 µA Max D High-Current Outputs Drive Up To D Low Power Consumption, 40-µA Max ICC

HC10

Abstract: SN54HC10 SN74HC10 SN74HC10D SN74HC10DBR SN74HC10DR SN74HC10DT SN74HC10N SN74HC10NSR
Contextual Info: SN54HC10, SN74HC10 TRIPLE 3ĆINPUT POSITIVEĆNAND GATES SCLS083D − DECEMBER 1982 − REVISED AUGUST 2003 D Wide Operating Voltage Range of 2 V to 6 V D Outputs Can Drive Up To 10 LSTTL Loads D Low Power Consumption, 20-µA Max ICC SN54HC10 . . . J OR W PACKAGE

hc166

Abstract: SN54HC166 SN74HC166 SN74HC166D SN74HC166DBR SN74HC166DR SN74HC166DT SN74HC166N SN74HC166NSR SN74HC166PW
Contextual Info: SN54HC166, SN74HC166 8ĆBIT PARALLELĆLOAD SHIFT REGISTERS SCLS117D − DECEMBER 1982 − REVISED SEPTEMBER 2003 D D D D D Wide Operating Voltage Range of 2 V to 6 V Outputs Can Drive Up To 10 LSTTL Loads Low Power Consumption, 80-µA Max ICC Typical tpd = 13 ns

SN54HC161

Abstract: SN74HC161 SN74HC161D SN74HC161DR SN74HC161DT SN74HC161N SN74HC161NSR SN74HC161PW SN74HC161PWR
Contextual Info: SN54HC161, SN74HC161 4ĆBIT SYNCHRONOUS BINARY COUNTERS SCLS297D − JANUARY 1996 − REVISED SEPTEMBER 2003 D D D D D Wide Operating Voltage Range of 2 V to 6 V Outputs Can Drive Up To 10 LSTTL Loads Low Power Consumption, 80-µA Max ICC Typical tpd = 14 ns

integrated circuit sn74hc164n diagram

Abstract: SN74HC164N
Contextual Info: SN54HC164, SN74HC164 8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS SCLS115C – DECEMBER 1982 – REVISED DECEMBER 2002 D D D D D D D D D SN54HC164 . . . J OR W PACKAGE SN74HC164 . . . D, N, NS, OR PW PACKAGE TOP VIEW Wide Operating Voltage Range of 2 V to 6 V