SMPTE CHECKFIELD PATTERN Search Results

SMPTE checkfield pattern

Abstract: GS9024 GS9035C GS9035CCPJ GS9035CCTJ TOKYO 243MHz filter
Contextual Info: * 1/,1; , GS9035C Serial Digital Reclocker DATA SHEET DESCRIPTION • adjustment-free operation The GS9035C is a high performance clock and data recovery IC designed for serial digital data. The GS9035C receives either single-ended or differential PECL data and

EB9035A

Contextual Info: GENLINX II GS9035A Serial Digital Reclocker PRELIMINARY DATA SHEET DESCRIPTION • adjustment-free operation The GS9035A is a high performance clock and data recovery IC designed for serial digital data. The GS9035A receives either single-ended or differential PECL data and

Contextual Info: C3E IM IM U M C O R P O R A T I GEN LI N X OI M II GS9035 D jg jta | R e c |o c k e p PRELIMINARY DATA SHEET DEVICE DESCRIPTION STANDARD FEATURES adjustm ent-free operation auto-rate selection for 5 SMPTE data rates: 1 43,17 7, 270, 360, 540 Mb/s data rate indication output

GS7025

Abstract: GS7025-CQM GS7025-CTM GS9024 GS9025A GS9028 GS7025-CTME3 vlf receiver circuit Receiver 27MHz ROHS 241
Contextual Info: PRO-LINX GS7025 Serial Digital Receiver DATA SHEET DESCRIPTION • SMPTE 259M-C compliant 270Mb/s The GS7025 provides automatic cable equalization and high performance clock and data recovery for serial digital signals. The GS7025 receives either single-ended or

GS9024

Abstract: GS9025A GS9028 GS7025 GS7025-CQM GS7025-CTM GS9020
Contextual Info: 352/,1; GS7025 Serial Digital Receiver DATA SHEET DESCRIPTION • SMPTE 259M-C compliant 270Mb/s The GS7025 provides automatic cable equalization and high performance clock and data recovery for serial digital signals. The GS7025 receives either single-ended or

XILINX/HD-SDI over sd

Abstract: CTXIL103 smpte 424m to itu 656 smpte rp 198 3g hd sdi regenerator reclocker smpte 424m to smpte 274m Block diagram on monochrome tv transmitter 54 mhz crystal oscillator XAPP514 2048x1080
Contextual Info: Audio/Video Connectivity Solutions for Virtex-II Pro and Virtex-4 FPGAs Reference Designs for the Broadcast Industry: Volume 1 XAPP514 v4.0.1 October 15, 2008 R R Xilinx is disclosing this Document and Intellectual Property (hereinafter “the Design”) to you for use in the development of