silego
Abstract: Silego Technology PC3200 Q11A Q13A SSTVN16859 SLGVF857
Contextual Info: SLGSSTVF16859C DDR1 13 to 26 Bit Low Noise Registered Buffer Applications: • PC1600/2100/2700/3200 DDR memory modules • 1:2 Outputs ideal for stacked DDR DIMMS • Provides a complete low power / low noise solution together with the SLGVF857C-14 PLL buffer
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SLGSSTVF16859C
PC1600/2100/2700/3200
SLGVF857C-14
SLGSSTVF16859CF
silego
Silego Technology
PC3200
Q11A
Q13A
SSTVN16859
SLGVF857
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silego
Abstract: Silego Technology SLGVF857C-14 48-TVSOP SLGVF857 CVF857 PC3200 DDR400 40-VFQFN SLGVF857C
Contextual Info: SLGVF857C-14 2.5V Low Power PLL Clock Driver for DDR1 2.5 Features: • 1:10 SSTL2 diffrential clock distribution • Environmentally GREEN packaging process • PLL tracks spread spectrum modulation • Powerdown mode when PWRDWN low or CLK stopped • 2.3V-2.7V Operation for PC1600/2100/2700
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SLGVF857C-14
PC1600/2100/2700
PC3200
60MHz
220MHz
CVF857
JESD82-1A
silego
Silego Technology
SLGVF857C-14
48-TVSOP
SLGVF857
CVF857
PC3200
DDR400
40-VFQFN
SLGVF857C
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PDF
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INSSTE32882
Abstract: maxim dallas 2501 P16CV SY100EL16 SN65MLVD201 SN65EPT22 INCU877 INCUA877 ttl crystal oscillator using 7404 P16CV857B
Contextual Info: Clocks and Timing Guide www.ti.com/clocks 2Q 2009 2 Clocks and Timing Guide ➔ Clocks and Timing Selection Tree Clocks by Function Clock Distribution Non- PLL Fanout Buffers PLL Buffers RF Synthesizers Clock Generation General Purpose Generator/Synthesizer
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INSSTE32882
Abstract: maxim dallas 2501 insstua32866 INSSTU32864 INSSTU32866 ttl crystal oscillator using CIRCUIT DIAGRAM INCUA877 ps 2501 dallas GSM home automation block diagram INCU877
Contextual Info: Clocks and Timing Guide www.ti.com/clocks 2Q 2009 2 Clocks and Timing Guide ➔ Clocks and Timing Selection Tree Clocks by Function Clock Distribution Non- PLL Fanout Buffers PLL Buffers RF Synthesizers Clock Generation General Purpose Generator/Synthesizer
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PDF
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