SKEW11 Search Results

Contextual Info: * DUAL SUPPLY SYNERGY o c ta l e c l-to -ttl S E M IC O N D U C T O R Clockworks s y io o h a b « SY100HA643 DESCRIPTION FEATURES E C L /T T L v e rs io n o f p o p u la r E C L in P S ™ E 1 11 4 0 0 p s w ith in d e v ic e sk ew 8 0 0 p s p a rt-to -p a rt s k e w

Contextual Info: * S IN G L E S U P P L Y O C T A L SYNERGY Cloc* ° r* ™ P E C L /T T L -tO -T T L SY100H646 S E M IC O N D U C T O R FEATURES • PECL/TTL-to-TTL version of popular ECLinPS E111 ■ Meets specifications required to drive highperformance x86 processors

ic 192 ttl

Contextual Info: 3.3V SINGLE SUPPLY Q UAD V P E C L T O .T T I S YN ER G Y ° WITH LATCHED O UTPUT ENABLE S M tC O N D U C T O R Clockworks PRELIMINARY SY10H842L SY100H842L DESCRIPTION FEATURES • 3.3V power supply ■ Translates positive ECL to TTL PECL-to-TTL ■ 300ps pin-to-pin skew

Contextual Info: SING LE SUPPLY Q U A D P EC L-TO -TTL Clockworks SY10H842 W /LA TC H E D O UTPUT E N A B L E sÈ llb ólÌD U C T O R SY100H842 DESCRIPTION FEATURES • Translates positive ECL to TTL PECL-to-TTL ■ 300ps pin-to-pin skew ■ 500ps part-to-part skew ■ Differential internal design for increased noise

CY7B9910

Abstract: CY7B9920
Contextual Info: fax id: 3516 CY7B9910 CY7B9920 Low Skew Clock Buffer Block Diagram Description Features • • • • • • • • • Phase Frequency Detector and Filter All outputs skew <100 ps typical 250 max. 15- to 80-MHz output operation Zero input to output delay

metal case REGULATOR IC 7812 pin diagram

Abstract: CY7C4275 CY7C4285 CY7C42X5
Contextual Info: fax id: 5416 ^;aaazgg st CY7C4275 CY7C4285 PRELIMINARY ; U I F lm c b ti 32K/64Kx18 1 Meg Deep Sync FIFOs Functional Description Features H ig h-speed , low -pow er, first-in first-o u t F IF O m em o ries 32K x 18 (C Y 7 C 42 75 ) 64K x 18 (C Y 7 C 42 85 )

Contextual Info: fax id: 3516 CY7B9910 CY7B9920 •■mmmmggf ¿mw Low Skew Clock Buffer Block Diagram Description Features • • • • • • • • • Phase Frequency Detector and Filter All outputs skew <100 ps typical 250 max. 15- to 80-MHz output operation Zero input to output delay

Contextual Info: fax id: 3529 CY2961 Pentium and Cyrix® Compatible Clock Synthesizer/Driver with SDRAM Support Features • * * • • Pin for pin replacement for the ICW48C61-01, ICS9169C-23, and PLL52C61-01 -1 Option • Complete clock solution to meet requirements of

V4838

Contextual Info: H PER!COM PI74LCX16373 Miiiiiiiiiiiiiiiiiii iii iii iii iii iii ii iii iii iii iii iii iii iii iii iii Fast CMOS 3.3V 16-Bit Transparent Latch Product F eatures: Product Description: • Functionally compatible with FCT3, LVT, and 74 series 16373 families of products

Contextual Info: * SY N ER G Y S V' ! f i b 1 h 7 Q U A D 2 1 M U L T I PL E KEF; V 1ODE 1 S7 S E M IC O N D U C T O R FEATURES • Individual select controls ■ Extended 100E V e e range of -4 .2 V to -5 .5 V ■ 550ps max. D to Output ■ 800ps max. SEL to Output DESCR

Contextual Info: f¡J PER ICOM l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l i l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l Fast CMOS 3.3V 8-Bit Transparent Latch

XTCE

Abstract: oasi CY7C4282 CY7C4292 EF 6802 P
Contextual Info: fax id: 5419 CY7C4282 CY7C4292 PRELIMINARY 64K/128Kx9 Deep Sync FIFOs Features Functional Description • High-speed, low-power, first-in first-out FIFO memories • 64k x 9 (CY7C4282) • 128k x 9 (CY7C4292) • 0.5 micron CMOS for optimum speed/power • High-speed, Near Zero Latency (True Dual-Ported

Contextual Info: « DUAL SUPPLY SYNERGY OCTAL e c l - t o - t t l SEMICONDUCTOR Clockworks s y io o h a b « SY100HA643 DESCRIPTION FEATURES ECL/TTL version of popular ECLinPS™ E111 400ps within device skew 800ps part-to-part skew Latch Differential internal design V bb output

CY7C4282V

Abstract: CY7C4292V
Contextual Info: fax id: 5424 CYPRESS CY7C4282V CY7C4292V PRELIMINARY 64K/128Kx9 Low Voltage Deep Sync FIFOs w/ Retransmit & Depth Expansion Features Functional Description 3.3V o p e ratio n fo r low p o w er c o n su m p tio n and easy integration into low -vo itag e sy ste m s

Contextual Info: fax id: 5424 CY7C4282V CY7C4292V ^CYPRESS pmummm 64K/128Kx9 Low Voltage Deep Sync FIFOs w/ Retransmit & Depth Expansion Features Functional Description • 3.3V operation for low power consumption and easy integration into low voltage systems • High-speed, low-power, first-in first-out FIFO

Contextual Info: fax id: 5416 CY7C4275 CY7C4285 PRELIMINARY 32K/64Kx18 Deep Sync FIFOs Functional Description Features • H ig h -s p e ed , low -pow er, first-in firs t-o u t F IF O m em o ries • 32K x 18 (C Y 7 C 42 75 ) • 64K x 18 (C Y 7 C 42 85 ) • 0.5 m icron C M O S fo r o p tim u m s p e e d /p o w e r

Contextual Info: fax id: 5419 CYPRESS PRELIMINARY 64K/128K x9 Deep Sync FIFOs w/ Retransmit & Depth Expansion Features • • • • • High-speed, low-power, first-in first-out FIFO memories 64k x 9 (CY7C4282) 128k x 9 (CY7C4292) 0.5 micron CMOS for optimum speed/power

Contextual Info: fax id: 5419 CY7C4282 CY7C4292 PRELIMINARY 64K/128Kx9 Deep Sync FIFOs Features Functional Description • High-speed, low-power, first-in first-out FIFO memories • 64k x 9 (CY7C4282) • 128k x 9 (CY7C4292) • 0.5 micron CMOS for optimum speed/power • High-speed, Near Zero Latency (True Dual-Ported

Contextual Info: Freescale Semiconductor, Inc. TECHNICAL DATA 3.3 V 1:8 LVCMOS PLL Clock Generator The MPC9653A is a 3.3 V compatible, 1:8 PLL based clock generator and zero-delay buffer targeted for high performance low-skew clock distribution in mid-range to high-performance telecom, networking and computing

CY74FCT162244AT

Abstract: CY74FCT162244CT CY74FCT162244T CY74FCT16244AT CY74FCT16244CT CY74FCT16244T CY74FCT162H244AT CY74FCT162H244T
Contextual Info: *I TEXAS Data sheet acquired from Cypress Sem iconductor Corporation. Data sheet modified to remove devices not offered. H| _ nstrum ents SCCS028 - December 1987 - Revised March 2000 Features • FCT-E speed at 3.2 ns • Power-off disable outputs permits live insertion

Contextual Info: fax id: 5422 CY7C4255V/CY7C4265V CY7C4275V/CY7C4285V PRELIMINARY 8K/16K/32K/64Kx18 Low Voltage Deep Sync FIFOs Features Functional Description The CY7C4255/65/75/85V are high-speed, low-power, first-in first-out FIFO memories with clocked read and write interfac­

semi catalog

Abstract: j510 Motorola transistor smd marking codes rf choke cross comparison books TTL catalog IC Data-book MPC930 MPC9449 MPC951 MPC952
Contextual Info: Freescale Semiconductor Data Book. Advanced Clock Drivers. DL207 Rev. 2 8/2004 Advanced Clock Drivers Selector Guide 1 Clock Generator Data Sheets 2 QUICCClock Generator Data Sheets 3 Failover or Redundant Clock Data Sheets 4 Clock Synthesizer Data Sheets

P174lcx

Contextual Info: fr PERICOM II 11111111111111111111111111111111111 II 1111111111111111111111111 Fast CMOS 3.3V 8-Bit Buffer/Line Driver Product Features: Product Description: • Functionally compatible with FCT3, LVT, and 74

Contextual Info: fax id: 7046 3F CY74FCT16500T CY74FCT162500T CYPRESS 18-Bit Registered Transceiver Features Functional Description • Low power, pin com patible replacem ent for ABT functions • FCT-C speed at 4.6 ns • Power-off disable outputs permits live insertion