SDRAM 4 BANK 4096 16 Search Results

EM639325TS

Abstract: EM639325Ts-6g
Contextual Info: EtronTech EM639325TS 4M x 32 SDRAM Preliminary Rev 0.5 May/2007 Features • • • • • • • • • • • • Clock rate: 166 MHz Fully synchronous operation Internal pipelined architecture Four internal banks (1M x 32bit x 4bank) Programmable Mode

EM669325

Contextual Info: EtronTech EM669325BK 4M x 32 SDRAM Preliminary Rev 0.5 May/2007 Features • • • • Clock rate: 166 MHz Fully synchronous operation Internal pipelined architecture Four internal banks (1M x 32bit x 4bank) Programmable Mode - CAS# Latency: 3 - Burst Length: 1, 2, 4, 8, or full page

P-TSOPII-54

Contextual Info: HYB 39S128400/800/160DT L 128-MBit Synchronous DRAM 128-MBit Synchronous DRAM Preliminary Target Specification 10.01 High Performance: • Multiple Burst Read with Single Write Operation -6 -7 -7.5 -8 Units fCK 166 143 133 125 MHz • Automatic and Controlled Precharge

hx 2272 DECODER

Abstract: sdram 4 bank 4096 16 HM5212165LTD-10 HM5212165TD-10 HM5212805LTD-10 HM5212805TD-10 Hitachi DSA00196
Contextual Info: HM5212165 Series HM5212805 Series 128M LVTTL interface SDRAM 66 MHz 2-Mword x 16-bit × 4-bank/4-Mword × 8-bit × 4-bank ADE-203-881B Z Rev. 1.0 Jul. 10, 1998 Description The Hitachi HM5212165 is a 128-Mbit SDRAM organized as 2097152-word × 16-bit × 4-bank. The Hitachi

HM5212165DLTD-10

Abstract: sdram 4 bank 4096 16 HM5212165DTD-10 HM5212805DLTD-10 HM5212805DTD-10 Hitachi DSA00196
Contextual Info: HM5212165D Series HM5212805D Series 128M LVTTL interface SDRAM 66 MHz 2-Mword x 16-bit × 4-bank/4-Mword × 8-bit × 4-bank ADE-203-945 Z Preliminary Rev. 0.0 Aug. 4, 1998 Description The Hitachi HM5212165D is a 128-Mbit SDRAM organized as 2097152-word × 16-bit × 4-bank. The

Hitachi DSA002753

Contextual Info: HM5212165F-75/A60/B60 HM5212805F-75/A60/B60 [ 128M LVTTL interface SDRAM 133 MHz/100 MHz 2-Mword x 16-bit × 4-bank/4-Mword × 8-bit × 4-bank PC/133, PC/100 SDRAM ADE-203-1048 Z Preliminary Rev. 0.0 May. 17, 1999 Description The Hitachi HM5212165F is a 128-Mbit SDRAM organized as 2097152-word × 16-bit × 4-bank. The Hitachi HM5212805F is a 128-Mbit SDRAM organized as 4194304-word × 8-bit × 4-bank. All inputs and outputs are referred to the rising edge of the clock input. It is packaged in standard 54-pin plastic TSOP II.

HM5212805F-75A

Abstract: PC133-SDRAM Hitachi DSA00164 HM5212165F-75A
Contextual Info: HM5212165F-75A HM5212805F-75A 128M LVTTL interface SDRAM 133 MHz 2-Mword x 16-bit × 4-bank/4-Mword × 8-bit × 4-bank PC/133 SDRAM ADE-203-1049 Z Preliminary Rev. 0.0 May. 20, 1999 Description The Hitachi HM5212165F is a 128-Mbit SDRAM organized as 2097152-word × 16-bit × 4-bank. The Hitachi HM5212805F is a 128-Mbit SDRAM organized as 4194304-word × 8-bit × 4-bank. All inputs and outputs are referred to the rising edge of the clock input. It is packaged in standard 54-pin plastic TSOP II.

a60 GENERATOR

Abstract: Hitachi DSA00164
Contextual Info: HM5212165F-75/A60/B60 HM5212805F-75/A60/B60 128M LVTTL interface SDRAM 133 MHz/100 MHz 2-Mword x 16-bit × 4-bank/4-Mword × 8-bit × 4-bank PC/133, PC/100 SDRAM ADE-203-1048A Z Rev. 1.0 Jan. 31, 2000 Description The Hitachi HM5212165F is a 128-Mbit SDRAM organized as 2097152-word × 16-bit × 4-bank. The

Hitachi DSA00174

Contextual Info: HM5212165F-75/A60/B60 HM5212805F-75/A60/B60 128M LVTTL interface SDRAM 133 MHz/100 MHz 2-Mword x 16-bit × 4-bank/4-Mword × 8-bit × 4-bank PC/133, PC/100 SDRAM ADE-203-1048 Z Preliminary Rev. 0.0 May. 17, 1999 Description The Hitachi HM5212165F is a 128-Mbit SDRAM organized as 2097152-word × 16-bit × 4-bank. The

P-TSOPII-54

Abstract: PC133 registered reference design
Contextual Info: HYB 39S128400/800/160CT L 128-MBit Synchronous DRAM 128-MBit Synchronous DRAM • High Performance: • Multiple Burst Read with Single Write Operation -7 -7.5 -8 Units fCK 143 133 125 MHz • Automatic and Controlled Precharge Command tCK3 7 7.5 8 ns • Data Mask for Read/Write Control (x4, x8)

P-TSOPII-54

Abstract: caz smd PC133 registered reference design
Contextual Info: HYB 39S64400/800/160ET L 64-MBit Synchronous DRAM 64-MBit Synchronous DRAM Preliminary Datasheet • Automatic and Controlled Precharge Command • High Performance: -7 -7.5 -8 Units fCKMAX 143 133 125 MHz tCK3 7 7.5 8 ns tAC3 5.4 5.4 6 ns tCK2 7.5 10 10

HM5264805 Series

Abstract: HM5264165DTT-A60 sdram 4 bank 4096 16 Hitachi DSA00196
Contextual Info: HM5264165D-A60 HM5264805D-A60 HM5264405D-A60 64M LVTTL interface SDRAM 100 MHz 1-Mword x 16-bit × 4-bank/2-Mword × 8-bit × 4-bank /4-Mword × 4-bit × 4-bank PC/100 SDRAM ADE-203-909 Z Preliminary Rev. 0.0 May. 8, 1998 Description The Hitachi HM5264165D is a 64-Mbit SDRAM organized as 1048576-word × 16-bit × 4 bank. The Hitachi

Contextual Info: 64Mb: x4, x8, x16 SDRAM Features SDR SDRAM MT48LC16M4A2 – 4 Meg x 4 x 4 Banks MT48LC8M8A2 – 2 Meg x 8 x 4 Banks MT48LC4M16A2 – 1 Meg x 16 x 4 Banks Features Options • PC100- and PC133-compliant • Fully synchronous; all signals registered on positive

sdram 4 bank 4096 16

Abstract: HM5264165DTT-B60 Hitachi DSA00196
Contextual Info: HM5264165D-B60 HM5264805D-B60 HM5264405D-B60 64M LVTTL interface SDRAM 100 MHz 1-Mword x 16-bit × 4-bank/2-Mword × 8-bit × 4-bank /4-Mword × 4-bit × 4-bank PC/100 SDRAM ADE-203-908 Z Preliminary Rev. 0.0 May. 8, 1998 Description The Hitachi HM5264165D is a 64-Mbit SDRAM organized as 1048576-word × 16-bit × 4 bank. The Hitachi

39S64160BT-8

Abstract: SMD MARKING T5 application of sequential circuit CAZ MARKING marking RBY
Contextual Info: HYB 39S64400/800/160BT L 64-MBit Synchronous DRAM 64-MBit Synchronous DRAM • Multiple Burst Read with Single Write Operation • High Performance: • Automatic and Controlled Precharge Command -7.5 -8 Units fCKMAX 133 125 MHz tCK3 7.5 8 ns tAC3 5.4 6 ns

Contextual Info: 64Mb: x4, x8, x16 SDRAM Features SDR SDRAM MT48LC16M4A2 – 4 Meg x 4 x 4 Banks MT48LC8M8A2 – 2 Meg x 8 x 4 Banks MT48LC4M16A2 – 1 Meg x 16 x 4 Banks Features Options • PC100- and PC133-compliant • Fully synchronous; all signals registered on positive

Contextual Info: 64Mb: x4, x8, x16 SDRAM Features SDR SDRAM MT48LC16M4A2 – 4 Meg x 4 x 4 Banks MT48LC8M8A2 – 2 Meg x 8 x 4 Banks MT48LC4M16A2 – 1 Meg x 16 x 4 Banks Features Options • PC100- and PC133-compliant • Fully synchronous; all signals registered on positive

P-TSOPII-54

Abstract: Q67100-Q1838 Q67100-Q2781
Contextual Info: HYB 39S64400/800/160BT L 64-MBit Synchronous DRAM 64-MBit Synchronous DRAM • Multiple Burst Read with Single Write Operation • High Performance: • Automatic and Controlled Precharge Command -7.5 -8 Units fCKMAX 133 125 MHz tCK3 7.5 8 ns tAC3 5.4 6 ns

HM5264805LTT-B60

Abstract: HM5264805LTTB60 HM5264805TT-B60 Hitachi DSA00164
Contextual Info: HM5264165-B60 HM5264805-B60 HM5264405-B60 64M LVTTL interface SDRAM 100 MHz 1-Mword x 16-bit × 4-bank/2-Mword × 8-bit × 4-bank /4-Mword × 4-bit × 4-bank PC/100 SDRAM ADE-203-832D Z Rev. 2.0 Oct. 20, 1998 Description The Hitachi HM5264165 is a 64-Mbit SDRAM organized as 1048576-word × 16-bit × 4 bank. The Hitachi

sdram 4 bank 4096 16

Abstract: HM5264165DLTT-80 HM5264165DTT-80 HM5264805DTT-80 HM5264405DTT-80 Hitachi DSA00196 HM5264165DTT
Contextual Info: HM5264165D Series HM5264805D Series HM5264405D Series 64M LVTTL interface SDRAM 125 MHz/100 MHz 1-Mword x 16-bit × 4-bank/2-Mword × 8-bit × 4-bank/ 4-Mword × 4-bit × 4-bank ADE-203-910 Z Preliminary Rev. 0.0 May. 8, 1998 Description The Hitachi HM5264165D is a 64-Mbit SDRAM organized as 1048576-word × 16-bit × 4 bank. The Hitachi

Hitachi DSA00276

Contextual Info: HM5264165F-75A HM5264805F-75A HM5264405F-75A 64M LVTTL interface SDRAM 133 MHz 1-Mword x 16-bit × 4-bank/2-Mword × 8-bit × 4-bank /4-Mword × 4-bit × 4-bank PC/133 SDRAM ADE-203-1047 Z Preliminary Rev. 0.0 May. 17, 1999 Description The Hitachi HM5264165F is a 64-Mbit SDRAM organized as 1048576-word × 16-bit × 4 bank. The Hitachi

Hitachi DSA00164

Contextual Info: x HM52Y64165F Series HM52Y64805F Series HM52Y64405F Series 64M SDRAM 133 MHz/125 MHz 1-Mword x 16-bit × 4-bank/2-Mword × 8-bit × 4-bank /4-Mword × 4-bit × 4-bank ADE-203-974 Z Preliminary Rev. 0.0 Oct. 30, 1998 Description The Hitachi HM52Y64165F is a 64-Mbit SDRAM organized as 1048576-word × 16-bit × 4 bank. The Hitachi HM52Y64805F is a 64-Mbit SDRAM organized as 2097152-word × 8-bit × 4 bank. The Hitachi

Contextual Info: 64Mb: x4, x8, x16 SDRAM Features SDR SDRAM MT48LC16M4A2 – 4 Meg x 4 x 4 Banks MT48LC8M8A2 – 2 Meg x 8 x 4 Banks MT48LC4M16A2 – 1 Meg x 16 x 4 Banks Features Options Marking • Configuration – 16 Meg x 4 4 Meg x 4 x 4 banks – 8 Meg x 8 (2 Meg x 8 x 4 banks)

MT48LC8M16A2B4

Abstract: MT48LC16M8A2BB PC133 registered reference design
Contextual Info: Preliminary‡ 128Mb: x4, x8, x16 Automotive SDRAM Features Automotive SDR SDRAM MT48LC32M4A2 – 8 Meg x 4 x 4 Banks MT48LC16M8A2 – 4 Meg x 8 x 4 Banks MT48LC8M16A2 – 2 Meg x 16 x 4 Banks Features Options • PC100- and PC133-compliant • Fully synchronous; all signals registered on positive